FPGA Central - World's 1st FPGA / CPLD Portal

FPGA Central

World's 1st FPGA Portal

 

Go Back   FPGA Groups > NewsGroup > VHDL

VHDL comp.lang.vhdl newsgroup / Usenet

Reply
 
LinkBack Thread Tools Display Modes
  #1 (permalink)  
Old 10-07-2006, 09:07 PM
Guest
 
Posts: n/a
Default Inexplicable compilation error

Hello all,

I'm using Active HDL 6.3, student edition.

In the code below, I'm getting the following error:

# Error: COMP96_0078: full_adder.vhd : (22, 10): Unknown identifier
"std_logic".

This error occurs in the declaration of entity foo. Note that std_logic
is found just fine prior to this point in the declaration of entity
full_adder. What on earth is going on?

Thanks in advance,
Dave



library ieee;
use ieee.std_logic_1164.all;

entity full_adder is
port(
a, b, cin : in std_logic;
s, cout : out std_logic
);
end entity full_adder;

entity foo is
port(
f: in std_logic
);
end entity foo;

Reply With Quote
  #2 (permalink)  
Old 10-07-2006, 09:13 PM
Duane Clark
Guest
 
Posts: n/a
Default Re: Inexplicable compilation error

[email protected] wrote:
> Hello all,
>
> I'm using Active HDL 6.3, student edition.
>
> In the code below, I'm getting the following error:
>
> # Error: COMP96_0078: full_adder.vhd : (22, 10): Unknown identifier
> "std_logic".
>
> This error occurs in the declaration of entity foo. Note that std_logic
> is found just fine prior to this point in the declaration of entity
> full_adder. What on earth is going on?


It is one of the stranger things in VHDL. You need to redeclare the
libraries before each entity. That's just the way it works
Reply With Quote
  #3 (permalink)  
Old 10-09-2006, 07:26 PM
Andy
Guest
 
Posts: n/a
Default Re: Inexplicable compilation error

The scope of the context clause (library and use statements) is
independent of the file. It is limited to the design unit immediately
following, in this case: full_adder. Note that architectures and
package bodies inherit the scope of their associated entity and package
declaration, regardless of whether those secondary units are located in
the same file as their associated primary units.

This behavior was borrowed from ada.

Andy


[email protected] wrote:
> Hello all,
>
> I'm using Active HDL 6.3, student edition.
>
> In the code below, I'm getting the following error:
>
> # Error: COMP96_0078: full_adder.vhd : (22, 10): Unknown identifier
> "std_logic".
>
> This error occurs in the declaration of entity foo. Note that std_logic
> is found just fine prior to this point in the declaration of entity
> full_adder. What on earth is going on?
>
> Thanks in advance,
> Dave
>
>
>
> library ieee;
> use ieee.std_logic_1164.all;
>
> entity full_adder is
> port(
> a, b, cin : in std_logic;
> s, cout : out std_logic
> );
> end entity full_adder;
>
> entity foo is
> port(
> f: in std_logic
> );
> end entity foo;


Reply With Quote
Reply

Bookmarks

Thread Tools
Display Modes

Posting Rules
You may not post new threads
You may not post replies
You may not post attachments
You may not edit your posts

BB code is On
Smilies are On
[IMG] code is On
HTML code is Off
Trackbacks are On
Pingbacks are On
Refbacks are On


Similar Threads
Thread Thread Starter Forum Replies Last Post
mb-g++ compilation error with EDK 8.2.02i Bathala FPGA 0 02-13-2008 09:44 AM
MXE compilation error [email protected] FPGA 0 03-16-2007 03:09 PM
Error 10170 syntax error during compilation Jughead Verilog 3 08-28-2006 07:32 AM
Compilation error YesMann VHDL 2 08-08-2003 01:51 PM
Compilation error YesMann FPGA 2 08-08-2003 01:51 PM


All times are GMT +1. The time now is 08:57 AM.


Powered by vBulletin® Version 3.8.0
Copyright ©2000 - 2020, Jelsoft Enterprises Ltd.
Search Engine Friendly URLs by vBSEO 3.2.0
Copyright 2008 @ FPGA Central. All rights reserved