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-   -   Importing Structural VHDL into Cadence 4.4.6 (http://www.fpgacentral.com/group/showthread.php?t=66043)

Marcus Schaemann 09-17-2003 07:52 AM

Importing Structural VHDL into Cadence 4.4.6

I want to import my VHDL design (see below) into Cadence.
Synthesis with Synopsys Design Compiler creates a structural VHDL
I don't have much experience with Cadence, but I have Cadence libraries
with schematics and layout for the cell IN1, so I think I should be able

to import the structural VHDL into cadence. But vhdlin returns:

duluth: *E,1024: intermediate file path
/usr/local/cadence-ic446/tools/leapfrog/files/STD.ship/standard for
package STD.STANDARD (AST) does not exist.

I think I got a problem with the environment setting for the standard

- Does anybody has a hint for me where to find the right package
in the cadence installation or in the technology libraries?
- How must I modify my cds.lib or vhdl code?
- Anybody got more information about the Europractice Design Flow?



System Environment:

Synopsys: 2001.08
Cadence: 4.4.6
Technology: AMS HIT-KIT v3.4, 0.35 CMOS (through Europractice v13.0)


INCLUDE /usr/local/cadence-ic446/share/cdssetup/cds.lib
INCLUDE $AMS_DIR/artist/HK_0.35/cds.lib
DEFINE sample /usr/local/cadence-ic446/tools/dfII/samples/cdslib/sample
DEFINE std /usr/local/cadence-ic446/tools/leapfrog/files/STD.ship
DEFINE IEEE /usr/local/cadence-ic446/tools/leapfrog/files/IEEE.ship


library IEEE;
use IEEE.std_logic_1164.all;

entity inv is
port (
A : in std_logic;
Y : out std_logic);
end inv;

architecture data_flow of inv is
Y <= not A;
end data_flow;


library IEEE;
use IEEE.std_logic_1164.all;
library HRDLIB;
use HRDLIB.all;

entity inv is
port( A : in std_logic; Y : out std_logic);
end inv;

architecture GAT of inv is
U7 : IN1 port map( A => A, Q => Y)
end GAT;

Eyck Jentzsch 09-17-2003 11:00 AM

Re: Importing Structural VHDL into Cadence 4.4.6
Marcus Schaemann wrote:
> Hello,

> cds.lib:
> --------
> INCLUDE /usr/local/cadence-ic446/share/cdssetup/cds.lib

INCLUDE /usr/local/cadence-ic446/tools/leapfrog/files/cds.lib
> INCLUDE $AMS_DIR/artist/HK_0.35/cds.lib
> DEFINE sample /usr/local/cadence-ic446/tools/dfII/samples/cdslib/sample

and remove these two (they are defined in the cds.lib above)
> DEFINE std /usr/local/cadence-ic446/tools/leapfrog/files/STD.ship
> DEFINE IEEE /usr/local/cadence-ic446/tools/leapfrog/files/IEEE.ship



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