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Old 09-14-2003, 11:07 AM
Kelvin
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Default How to run a zero-delay simulation in a design with a RAM?

Hi, All:

When I generated the RAM model from the Fab's software, it contains all the
timing delay and checks.
After I put it into my chip and run gate-level simulation with
+delay_mode_zero (and +delay_mode_unit also),
the timing and checks become zero, but the outputs from the RAM is wrong.

I need to perform a zero-delay simulation to get the switching activity,
while my process library puts a delay of 1ns
in every gate, so is there any way to surpress this gate-delay while allow
the timing delay & checks in the RAM?

My simulator is NCVerilog.

Best Regards,
Kelvin





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Old 09-15-2003, 06:06 AM
Steven Sharp
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Default Re: How to run a zero-delay simulation in a design with a RAM?

"Kelvin" <[email protected]> wrote in message news:<[email protected]>...
> After I put it into my chip and run gate-level simulation with
> +delay_mode_zero (and +delay_mode_unit also),
> the timing and checks become zero, but the outputs from the RAM is wrong.
>
> I need to perform a zero-delay simulation to get the switching activity,
> while my process library puts a delay of 1ns
> in every gate, so is there any way to surpress this gate-delay while allow
> the timing delay & checks in the RAM?
>
> My simulator is NCVerilog.


NC-Verilog supports the compiler directives `delay_mode_zero,
`delay_mode_unit, `delay_mode_distributed, `delay_mode_path. There is
also `resetall (which resets all directives back to the default state).

These can be put in your source files in appropriate places to specify
the delay mode to be used for the modules that follow them. This allows
applying different delay modes to different components in the design,
which may meet your needs.
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