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-   -   how to proceed to know the value of power consumption for our design in vhdl (http://www.fpgacentral.com/group/showthread.php?t=69518)

[email protected] 09-13-2006 11:50 AM

how to proceed to know the value of power consumption for our design in vhdl
dear all,
i would like to know that how to calculate the power of the design or
program done in vhdl.
now a days i am proceeding in this way as iam using xilinx 8.1 and
modelsim xeIII 6.0.

1.creating the hdl file of the design of interest
2.checking syntax by keeping design in synthesis/implementation mode
3.creating a new test bench waveform or vhdl test bench.
4.saving the created test bench waveform
5.by keeping design in beheavioural simulation mode i am checking my
design functionality by seeing the tab genrerate expected simulation
6.afterwards i am creating timing constraints(depending on what factors
we heve to craete timing constraints clock,pad to setup etc?)
7.then implement design and verify constraints( is this necessary or
directly we can go for post route simulation with out doing this step
and assigning pin locations and re implement design and verify pin
8.then selecting post route simulation in the sources window tab and
selecting the testbench waveform or vhdl testbench in sources window
and i am right click ing the simlate post place and route i am checking
the generate vcd file )
and then i am double clikcing the simalte post place and route to
verify design using timing simulation).
9. then i am analysing power by using Xpower tool . but i am getting
only static power, dynamic power i am not getting . how to get dynamic

after which part of design process(i.e., after which of above steps i
will get .ncd file)
can i get more than one .ncd file if my design name is say adder.
adder.ncd, adder**.ncd ** may be any thing.
plz clarify my doubts as i am a beginner in vhdl
thanking you in anticipation

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