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i am having simple code in VHDL,
i am runing this in active hd 6.1,

the how to generate block diagram automatically for the given code
sir.

i.e this code is cascade of 3 flip-flops, so software to genetate
this

entity rsynch is
port(
clk : in STD_LOGIC;
reset : in STD_LOGIC;
d : in STD_LOGIC;
q : buffer STD_LOGIC
);
end rsynch;

--}} End of automatically maintained section

architecture arch_rsynch of rsynch is
signal temp1 : std_logic;
signal temp2 : std_logic;
begin
p1: process ( reset,clk)
begin
if reset = '1' then
q <= '0';
elsif (clk'event and clk ='1' ) then
temp1 <= d;
temp2 <= temp1;
q <=temp2;
end if ;
end process p1;

end arch_rsynch;

[email protected] wrote:

> the how to generate block diagram automatically for the given code

I would use the ise or quartus rtl viewer.

-- Mike Treseler

Mike Treseler wrote:

> I would use the ise or quartus rtl viewer.

Having seen what comes out of Quartus RTl viewer, I wouldn't!

Regards,

--
Mark McDougall, Engineer
Virtual Logic Pty Ltd, <http://www.vl.com.au>
21-25 King St, Rockdale, 2216
Ph: +612-9599-3255 Fax: +612-9599-3266

Mark McDougall wrote:
> Mike Treseler wrote:
>> I would use the ise or quartus rtl viewer.

> Having seen what comes out of Quartus RTl viewer, I wouldn't!

http://home.comcast.net/~mike_treseler/stack.pdf

looks ok to me

Mike Treseler wrote:

> looks ok to me

I haven't had much luck with my designs!

Regards,

--
Mark McDougall, Engineer
Virtual Logic Pty Ltd, <http://www.vl.com.au>
21-25 King St, Rockdale, 2216
Ph: +612-9599-3255 Fax: +612-9599-3266