FPGA Central

Hello,

I need to genearte a pulse for half of the clock cycle. for example if
clock = '1' then pulse= '1', if clock ='0' then pulse ='0'. So, I do
not want the pulse to be high for one clock period but only for half
of the clock period. I want to load the data into the buffer using
this pulse.

Regards,
John

john wrote:
> Hello,
>
> I need to genearte a pulse for half of the clock cycle. for example if
> clock = '1' then pulse= '1', if clock ='0' then pulse ='0'. So, I do
> not want the pulse to be high for one clock period but only for half
> of the clock period. I want to load the data into the buffer using
> this pulse.
>
First generate a single pulse, synchronous to the clock.
Then OR (or AND, according to taste on polarity) that pulse with the
original clock.
If your original "single pulse" runs for several clocks, this tactic
will give you a burst of clock pulses.
Some old TTL chips (74166) had the OR gate on-chip, to support this kind
of device.