FPGA Central - World's 1st FPGA / CPLD Portal

FPGA Central

World's 1st FPGA Portal

 

Go Back   FPGA Groups > NewsGroup > VHDL

VHDL comp.lang.vhdl newsgroup / Usenet

Reply
 
LinkBack Thread Tools Display Modes
  #1 (permalink)  
Old 10-16-2003, 08:31 PM
youngsun park
Guest
 
Posts: n/a
Default goto statement is recommened in systemc?

I am looking at some systemc code and found that
goto is used pretty frequently.

Anybody has some idea about if it is good
practice or not?

I heard that a guy proved that you can program without
goto statement. Is it still valid in hardware modeling
like systemc?


-young.
Reply With Quote
  #2 (permalink)  
Old 11-14-2003, 09:15 AM
Marion McCoskey
Guest
 
Posts: n/a
Default Re: goto statement is recommened in systemc?

On 16 Oct 2003 11:31:26 -0700, [email protected] (youngsun park)
wrote:

>I am looking at some systemc code and found that
>goto is used pretty frequently.
>
>Anybody has some idea about if it is good
>practice or not?
>
>I heard that a guy proved that you can program without
>goto statement.


You can, but there are times when you can't create code that is as
small or fast without using the goto. It's probably good practice to
avoid goto when you can use other functions and get the same results.
Gotos are not as readable.

> Is it still valid in hardware modeling
>like systemc?


I'll have to pass on that one. Although I think it would depend on
the exact problem and the data dependencies involved. Hardware allows
parallelism that software does not because of the sequential nature of
the processor. Also, I have never used systemc.

Marion McCoskey
http://www.mcky.net
Reply With Quote
  #3 (permalink)  
Old 11-18-2003, 04:47 PM
David Pursley
Guest
 
Posts: n/a
Default Re: goto statement is recommened in systemc?

Whether goto's can be synthesized or not depends on your synthesis
tool. But to answer your original question, goto's are not
recommended in SystemC. That's certainly true for synthesis, and it's
a good idea in C/C++ in general, as well.

If you're interested in learning more about SystemC, I'd suggest
looking into the free SystemC online training on our website:

http://LearnSystemC.ForteDS.com

===================
David Pursley
Forte Design Systems (http://www.ForteDS.com)


Marion McCoskey <[email protected]> wrote in message news:<[email protected]>. ..
> On 16 Oct 2003 11:31:26 -0700, [email protected] (youngsun park)
> wrote:
>
> >I am looking at some systemc code and found that
> >goto is used pretty frequently.
> >
> >Anybody has some idea about if it is good
> >practice or not?
> >
> >I heard that a guy proved that you can program without
> >goto statement.

>
> You can, but there are times when you can't create code that is as
> small or fast without using the goto. It's probably good practice to
> avoid goto when you can use other functions and get the same results.
> Gotos are not as readable.
>
> > Is it still valid in hardware modeling
> >like systemc?

>
> I'll have to pass on that one. Although I think it would depend on
> the exact problem and the data dependencies involved. Hardware allows
> parallelism that software does not because of the sequential nature of
> the processor. Also, I have never used systemc.
>
> Marion McCoskey
> http://www.mcky.net

Reply With Quote
Reply

Bookmarks

Thread Tools
Display Modes

Posting Rules
You may not post new threads
You may not post replies
You may not post attachments
You may not edit your posts

BB code is On
Smilies are On
[IMG] code is On
HTML code is Off
Trackbacks are On
Pingbacks are On
Refbacks are On


Similar Threads
Thread Thread Starter Forum Replies Last Post
systemc Ron Baker, Pluralitas! FPGA 4 04-16-2006 07:42 PM
Case statement in systemC prem Verilog 1 02-01-2006 02:17 PM
how to suspend a module in the middle of its operation (or how to implement C 'goto' statement in Verilog) thomasc Verilog 1 04-28-2005 06:39 PM
why systemc? [email protected] Verilog 15 12-06-2004 11:41 AM
goto statement is recommened in systemc? youngsun park Verilog 2 11-18-2003 04:47 PM


All times are GMT +1. The time now is 09:26 PM.


Powered by vBulletin® Version 3.8.0
Copyright ©2000 - 2020, Jelsoft Enterprises Ltd.
Search Engine Friendly URLs by vBSEO 3.2.0
Copyright 2008 @ FPGA Central. All rights reserved