FPGA Central - World's 1st FPGA / CPLD Portal

FPGA Central

World's 1st FPGA Portal

 

Go Back   FPGA Groups > NewsGroup > VHDL

VHDL comp.lang.vhdl newsgroup / Usenet

Reply
 
LinkBack Thread Tools Display Modes
  #1 (permalink)  
Old 10-29-2003, 04:15 AM
INFO
Guest
 
Posts: n/a
Default Final Call for Papers

Final Call for Papers

ISQED 2004
5th International Symposium on

QUALITY
ELECTRONIC
DESIGN

March 22-24, 2004
San Jose, CA, USA

http://www.isqed.org

ISQED is the leading international conference dealing with the design for
manufacturability and quality issues front-to-back. ISQED spans three days,
Monday through Wednesday, in three parallel tracks, hosting near 100
technical presentations, six keynote speakers, two-three panel discussions,
workshops /tutorials and other informal meetings.


Please note the following important dates:

Paper Submission Deadline October 31, 2003
Acceptance Notifications November 17-19, 2003
Final Camera-Ready paper December 15, 2003

Papers are requested in the following areas:

Design for Manufacturability & Quality (DFMQ)
Analysis, modeling, and abstraction of manufacturing process parameters and
effects for highly predictable silicon performance. Design and synthesis of
high complexity ICs: signal integrity, transmission line effects, OPC,
phase shifting, and sub-wavelength lithography, manufacturing yield and
technology capability. Design for diagnosability, defect detection and
tolerance; self-diagnosis, calibration and repair. Design and
manufacturabilty issues for Digital, analog, mixed signal, RF, MEMS,
opto-electronic, biochemical-electronic, and nanotechnology based ICs.
Redundency and other yield improving techniques. Design quality definitions
and standards; design quality metrics to track and assess the quality of
electronic circuit design, as well as the quality of the design process
itself; design quality assurance techniques. Global, social, and economic
implications of design quality. Design metrics, methodologies and flows for
custom, semi-custom, ASIC, FPGA, RF, memory, networking circuit, etc. with
emphasis on quality. Design metrics and quality standards for SoC, and SiP.

Package - Design Interactions & Co-Design (PDI)
Concurrent circuit and package design and effect on quality. Packaging
electrical and thermal modeling and simulation for improved quality of
product. SoC versus system in a package (SiP): design and technology
solutions and tradeoffs; MCM and other packaging techniques; heat sink
technology.

Design Verification and Design for Testability (DVFT)
Hardware and Software, formal and simulation based design verification
techniques to ensure the functional correctness of hardware early in the
design cycle. DFT and BIST for digital and SoC. DFT for analog/mixed-signal
ICs and systems-on-chip, DFT/BIST for memories. Test synthesis and
synthesis for testability. DFT economics, DFT case studies. DFT and ATE.
Fault diagnosis, IDDQ test, novel test methods, effectiveness of test
methods, fault models and ATPG, and DPPM prediction. SoC/IP testing
strategies.

Robust Device, Interconnect, and Circuits (RDIC)
Device, substrate, interconnect, circuit , and IP block modeling and
simulation techniques; quality metrics, model order reduction; CMOS,
Bipolar, and SiGe HBTs device modeling in the context of advanced digital,
RF and high-speed circuits. Modeling and simulation of novel device and
interconnect concepts. Signal integrity analysis: coupling, inductive and
charge sharing noise; noise avoidance techniques. Power grid design,
analysis and optimization; timing analysis and optimization; thermal
analysis and design techniques for thermal management. Modeling statistical
process variations to improve design margin and robustness, use of
statistical circuit simulators. Power-conscious design methodologies and
tools; low power devices, circuits and systems; power-aware computing and
communication; system-level power optimization and management. Design
techniques for leakage current management.

EDA Tools & IP Blocks; Interoperability and Implications (EDA)
EDA tools addressing design quality. EDA tools interoperability issues and
implications. Management of design process, and design database. Effect of
emerging processes & devices on design flows, tools, and tool
interoperability. Emerging EDA standards. EDA design methodologies and
tools that address issues which impact the quality of the realization of
designs into physical integrated circuits. Tools and methods for comparison
of libraries and hard IP blocks. Challenges and solutions of the
integration, testing, and qualifying of multiple IP blocks. IP authoring
tools and methodologies. Methods and tools for design and maintenance of
technology independent hard and soft IP blocks. IP modeling and
abstraction. Risk management of IP reuse. Third party testing of IP blocks.

Physical Design, Methodologies & Tools (PDM)
Physical synthesis flows for correct-by-construction quality silicon,
implementation of large SoC designs. Tool frameworks and datamodels for
tightly integrated incremental synthesis, placement, routing, timing
analysis and verification. Placement, optimization, and routing techniques
for noise sensitivity reduction and fixing. Algorithms and flows for
harnessing crosstalk-delay during physical synthesis. Tool flows and
techniques for antenna rule and electromigration rule avoidance and fixing.
Spare-cell strategies for ECO, decoupling capacitance and antenna rule
fixing. Planning tools for predictable high-current, low-voltage power
distribution. Reliable clock tree generation and clock distribution
methodologies for Gigahertz designs. EDA tools, design techniques, and
methodologies, dealing with issues such as: timing closure, R, L, C
extraction, ground/Vdd bounce, signal noise/cross-talk /substrate noise,
voltage drop, power rail integrity, electromigration, hot carriers, EOS/ESD,
plasma induced damage and other yield limiting effects, high frequency
effects, thermal effects, power estimation, EMI/EMC, proximity correction &
phase shift methods, verification (layout, circuit, function, etc.).

Effects of Technology on IC Design, Performance, Reliability, and Yield
(TRD)
Effect of emerging processes & devices on design's time to market, yield,
reliability, and quality. Emerging issues in DSM CMOS: e.g. sub-threshold
leakage, gate leakage, technology road mapping and technology extrapolation
techniques. New and novel technologies such as SOI, Double-Gate(DG)-MOSFET,
Gate-All-Around (GAA)-MOSFET, Vertical-MOSFET, strained CMOS, high-bandwidth
metallization, etc. Challenges of mixed-signal design in digital CMOS or
BiCMOS technology, including issues of substrate coupling, cross-talk and
power supply noise. Significance of reliability effects such as gate oxide
integrity, electromigration, ESD, etc., in relation to electronic design.
Impacts of process technologies on circuit design and capabilities (e.g.
low-Vt transistors versus increased off-state leakages) and the accuracy,
use and implementation of SPICE models that faithfully reflect process
technologies. Successful applications of TCAD to circuit design.

Submission of Papers
Authors should submit FULL-LENGTH, original, unpublished papers (Minimum 4,
maximum 6 pages). To permit a blind review, do not include name(s) or
affiliation(s) of the author(s) on the manuscript and abstract. Submit your
papers using the on-line paper submission procedure available in the ISQED
web site. Please check the as-printed appearance of your paper before
submitting the paper. In case of any problems email the following 3 files to
[email protected]; i) The Full-length Manuscript in PDF ii) A 200 Words
Abstract and iii) A Cover Letter (not need if submitting on-line). Cover
letter must include:

I Title of the paper
II Name, affiliation, complete mailing address and phone, fax, and email of
the first author
III Name, affiliations, city, state, country of additional authors
IV Person to whom correspondence should be sent, if other than the 1st
author
V Identification as invited paper if applicable
VI Suggested area (as listed in previous page)

The guidelines for the final paper format is provided on the conference web
site at www.isqed.org.

Please note the following important dates:

Paper Submission Deadline October 31, 2003
Acceptance Notifications November 17-19, 2003
Final Camera-Ready paper December 15, 2003


About ISQED
The International Symposium on Quality Electronic Design (ISQED), is a
premier Design & Design Automation conference, aimed at bridging the gap
between and integration of, electronic design tools and processes,
integrated circuit technologies, processes & manufacturing, to achieve
design quality. ISQED is the pioneer and leading conference dealing with
design for manufacturability and quality issues front-to-back. The
conference provides a forum to present and exchange ideas and to promote the
research, development, and application of design techniques & methods,
design processes, and EDA design methodologies and tools that address issues
which impact the quality of the realization of designs into physical
integrated circuits. The conference attendees are primarily designers of the
VLSI circuits & systems (IP & SoC), those involved in the research,
development, and application of EDA/CAD Tools & design flows, process/device
technologists, and semiconductor manufacturing specialists including
equipment vendors. ISQED emphasizes a holistic approach toward design
quality and intends to highlight and accelerate cooperation among the IC
Design, EDA, Semiconductor Process Technology and Manufacturing communities.



Reply With Quote
Reply

Bookmarks

Thread Tools
Display Modes

Posting Rules
You may not post new threads
You may not post replies
You may not post attachments
You may not edit your posts

BB code is On
Smilies are On
[IMG] code is On
HTML code is Off
Trackbacks are On
Pingbacks are On
Refbacks are On


Similar Threads
Thread Thread Starter Forum Replies Last Post
ISQED09 Final Call for Papers ISQED Verilog 0 10-22-2008 12:22 AM
ISQED09 Final Call for Papers ISQED FPGA 0 10-22-2008 12:21 AM
Final call for papers john FPGA 0 01-12-2008 11:28 PM
Final call for papers - ISQED08 SVTI Verilog 0 10-28-2007 07:25 PM
Final Call for Papers INFO Verilog 0 10-29-2003 04:15 AM


All times are GMT +1. The time now is 02:16 AM.


Powered by vBulletin® Version 3.8.0
Copyright ©2000 - 2020, Jelsoft Enterprises Ltd.
Search Engine Friendly URLs by vBSEO 3.2.0
Copyright 2008 @ FPGA Central. All rights reserved