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  #1 (permalink)  
Old 09-19-2003, 09:46 AM
Sajan
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Default Dumping real signals in VCD

Hi
I am dumping signals which are declared as integer and real.
But i cant find these signals in the dump file.
Can anyone tell me why this happens and how to over this.
Regards,
Sajan.
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  #2 (permalink)  
Old 09-19-2003, 06:11 PM
Sajan
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Default Re: Dumping real signals in VCD

Well i forgot to mention that I am using Modelsim to do this.


[email protected] (Sajan) wrote in message news:<[email protected] com>...
> Hi
> I am dumping signals which are declared as integer and real.
> But i cant find these signals in the dump file.
> Can anyone tell me why this happens and how to over this.
> Regards,
> Sajan.

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  #3 (permalink)  
Old 09-20-2003, 05:20 PM
Ajeetha Kumari
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Default Re: Dumping real signals in VCD

Sajan,
Not sure if you are talking about VHDL or Verilog, either way
Modelsim can
probe real signals/variables in its waveform. When you say "VCD" how
do you create your VCD? That may be where the problem is, can you show
us how you dump VCD?

Ajeetha
http://www.noveldv.com

[email protected] (Sajan) wrote in message news:<[email protected] com>...
> Well i forgot to mention that I am using Modelsim to do this.
>
>
> [email protected] (Sajan) wrote in message news:<[email protected] com>...
> > Hi
> > I am dumping signals which are declared as integer and real.
> > But i cant find these signals in the dump file.
> > Can anyone tell me why this happens and how to over this.
> > Regards,
> > Sajan.

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  #4 (permalink)  
Old 09-22-2003, 09:03 AM
Sajan
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Default Re: Dumping real signals in VCD

Hi
I am using VHDL.
I use the following commands in the modelsim commandline
interface to dump the signals.

vcd file dump.vcd
vcd add /top/* /*I assume this means dump all signals */

I can see real signals in the wlf format of Modelsim but not in the VCD format
in which am trying to dump the signals.

Thanks and Regards,
Sajan.


[email protected] (Ajeetha Kumari) wrote in message news:<[email protected] com>...
> Sajan,
> Not sure if you are talking about VHDL or Verilog, either way
> Modelsim can
> probe real signals/variables in its waveform. When you say "VCD" how
> do you create your VCD? That may be where the problem is, can you show
> us how you dump VCD?
>
> Ajeetha
> http://www.noveldv.com
>
> [email protected] (Sajan) wrote in message news:<[email protected] com>...
> > Well i forgot to mention that I am using Modelsim to do this.
> >
> >
> > [email protected] (Sajan) wrote in message news:<[email protected] com>...
> > > Hi
> > > I am dumping signals which are declared as integer and real.
> > > But i cant find these signals in the dump file.
> > > Can anyone tell me why this happens and how to over this.
> > > Regards,
> > > Sajan.

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  #5 (permalink)  
Old 09-23-2003, 08:39 AM
Ajeetha Kumari
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Default Re: Dumping real signals in VCD

Sajan,
You seem to be correct, some how the "vcd add" misses out real
signals in VHDL. Initially I tried a Verilog example, that worked fine
with vcd add command. Looks like only the VHDL part of it has some
issue.

Sorry, couldn't be of much help, perhaps contact Modelsim support? Why
do you prefer VCD against WLF?

> vcd add /top/* /*I assume this means dump all signals */
>


This adds all signals in top instance, use with -r if you want the
whole hierarchy (I guess you know that already).

Ajeetha
http://www.noveldv.com

[email protected] (Sajan) wrote in message news:<[email protected] com>...
> Hi
> I am using VHDL.
> I use the following commands in the modelsim commandline
> interface to dump the signals.
>
> vcd file dump.vcd
> vcd add /top/* /*I assume this means dump all signals */
>
> I can see real signals in the wlf format of Modelsim but not in the VCD format
> in which am trying to dump the signals.
>
> Thanks and Regards,
> Sajan.

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  #6 (permalink)  
Old 09-23-2003, 03:54 PM
Sajan
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Posts: n/a
Default Re: Dumping real signals in VCD

Hi
Thanks for the effort.
I am modeling a Digital to analog converter in VHDL and the output of
the module is expected to be a real signal which is a sinewave.
I want to see the sinewave in the waveform. Somehow modelsim wave
window does not show a smooth transition from one signal level to the
other. So I want to dump it in VCD and then open it using other
waveform viewer like signal-scan.
Well thats the basic idea.
Cheers,
Sajan.

[email protected] (Ajeetha Kumari) wrote in message news:<[email protected] com>...
> Sajan,
> You seem to be correct, some how the "vcd add" misses out real
> signals in VHDL. Initially I tried a Verilog example, that worked fine
> with vcd add command. Looks like only the VHDL part of it has some
> issue.
>
> Sorry, couldn't be of much help, perhaps contact Modelsim support? Why
> do you prefer VCD against WLF?
>
> > vcd add /top/* /*I assume this means dump all signals */
> >

>
> This adds all signals in top instance, use with -r if you want the
> whole hierarchy (I guess you know that already).
>
> Ajeetha
> http://www.noveldv.com
>
> [email protected] (Sajan) wrote in message news:<[email protected] com>...
> > Hi
> > I am using VHDL.
> > I use the following commands in the modelsim commandline
> > interface to dump the signals.
> >
> > vcd file dump.vcd
> > vcd add /top/* /*I assume this means dump all signals */
> >
> > I can see real signals in the wlf format of Modelsim but not in the VCD format
> > in which am trying to dump the signals.
> >
> > Thanks and Regards,
> > Sajan.

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  #7 (permalink)  
Old 09-23-2003, 04:29 PM
Alan Fitch
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Posts: n/a
Default Re: Dumping real signals in VCD


"Sajan" <[email protected]> wrote in message
news:[email protected] om...
> Hi
> Thanks for the effort.
> I am modeling a Digital to analog converter in VHDL and the output

of
> the module is expected to be a real signal which is a sinewave.
> I want to see the sinewave in the waveform. Somehow modelsim wave
> window does not show a smooth transition from one signal level to

the
> other.


Have you tried selecting "analog interpolated" in Modelsim?

regards

Alan

--
Alan Fitch
Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * Perl * Tcl/Tk * Verification * Project
Services

Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, Hampshire, BH24
1AW, UK
Tel: +44 (0)1425 471223 mail:
[email protected]
Fax: +44 (0)1425 471573 Web:
http://www.doulos.com

The contents of this message may contain personal views which are not
the
views of Doulos Ltd., unless specifically stated.

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  #8 (permalink)  
Old 09-24-2003, 12:49 PM
Sajan
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Posts: n/a
Default Re: Dumping real signals in VCD

Thanks , I didnt know about that option.
Am able to get what I need using interpolated option.

Regards,
Sajan.

"Alan Fitch" <[email protected]> wrote in message news:<[email protected]>...
> "Sajan" <[email protected]> wrote in message
> news:[email protected] om...
> > Hi
> > Thanks for the effort.
> > I am modeling a Digital to analog converter in VHDL and the output

> of
> > the module is expected to be a real signal which is a sinewave.
> > I want to see the sinewave in the waveform. Somehow modelsim wave
> > window does not show a smooth transition from one signal level to

> the
> > other.

>
> Have you tried selecting "analog interpolated" in Modelsim?
>
> regards
>
> Alan
>
> --
> Alan Fitch
> Consultant
>
> DOULOS - Developing Design Know-how
> VHDL * Verilog * SystemC * Perl * Tcl/Tk * Verification * Project
> Services
>
> Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, Hampshire, BH24
> 1AW, UK
> Tel: +44 (0)1425 471223 mail:
> [email protected]
> Fax: +44 (0)1425 471573 Web:
> http://www.doulos.com
>
> The contents of this message may contain personal views which are not
> the
> views of Doulos Ltd., unless specifically stated.

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