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Old 09-24-2003, 02:34 AM
shumon
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Default dummy projects in VHDL/Verilog

As a person, who is does backend(post-RTL) ASIC design every
day(synthesis,scan-jtag-bist insertion,validation and
verification,place&route,timing analyses,DRC/LVS etc), I have lost
touch with the world of front-end RTL coding...something that I quite
enjoyed at school.

Is there a web-page/resource with decent size VHDL/Verilog projects
listed
(I mean proper "specs") that I can use, to code for fun ? I know,
checking out university sites for their Masters projects might be a
good idea..but does any of you, have any other pointers ??

Any help will be appreciated.

-Eager to code/Shumon.
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Old 09-24-2003, 02:41 AM
Jim Wu
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Default Re: dummy projects in VHDL/Verilog

Try www.opencores.org

Jim Wu
[email protected] (remove capital letters)
http://www.geocities.com/jimwu88/chips

"shumon" <[email protected]> wrote in message
news:[email protected] om...
> As a person, who is does backend(post-RTL) ASIC design every
> day(synthesis,scan-jtag-bist insertion,validation and
> verification,place&route,timing analyses,DRC/LVS etc), I have lost
> touch with the world of front-end RTL coding...something that I quite
> enjoyed at school.
>
> Is there a web-page/resource with decent size VHDL/Verilog projects
> listed
> (I mean proper "specs") that I can use, to code for fun ? I know,
> checking out university sites for their Masters projects might be a
> good idea..but does any of you, have any other pointers ??
>
> Any help will be appreciated.
>
> -Eager to code/Shumon.



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