FPGA Central

Hi, how are we all??

Im looking for some help / tips....

Could somone help me design a divide by 2 counter using VHDL.

Im looking to divide a clock input by 2, 4, 6, and 8...

Any help would be greatly appreciated

Ash12 wrote:
> Hi, how are we all??
>
> Im looking for some help / tips....
>
> Could somone help me design a divide by 2 counter using VHDL.

Define a variable of appropriate width. At reset, set it and the output
to 0. At each clock cycle, add one to the variable. When it's equal to
the number you want to divide by, reset it to 0 and toggle the output.

> Im looking to divide a clock input by 2, 4, 6, and 8...

The same basic code works for more or less arbitrary numbers. Note that
if you're coding for something like a recent FPGA, you may be able to
use a built-in clock manager instead of building it yourself.

--
Later,
Jerry.

The universe is a figment of its own imagination.

Further u can devide the clock by lpm_counter of multibit output.
bit 0 will be a clock devide by 2.
Bit 1 will be a clock devide by 4.
Bit 2 will be a clock devide by 8.

For clock devide by 6 u can use the vhdl code as


PROCESS (reset, clk16mh_b) --PROCESS no 1
BEGIN
IF reset = '0' THEN
count <= 0 ;
clk8mh_s <= '0' ;
ELSIF rising_edge(clk16mh_b) THEN
count <= count + 1 ;
IF count = (devideby/2)-1 THEN
clk8mh_s <= NOT clk8mh_s ;
count <= 0 ;
END IF ;
END IF ;
END PROCESS ;
clk8mh <= clk8mh_s ;

"devideby" is a constant that can be instantiated in generic.

I think it should be helpful.