FPGA Central - World's 1st FPGA / CPLD Portal

FPGA Central

World's 1st FPGA Portal

 

Go Back   FPGA Groups > NewsGroup > VHDL

VHDL comp.lang.vhdl newsgroup / Usenet

Reply
 
LinkBack Thread Tools Display Modes
  #1 (permalink)  
Old 11-23-2006, 03:38 AM
Guest
 
Posts: n/a
Default Creating a delay with VHDL without using wait (n00b)

Let me begin by saying that I am new to VHDL.

I would like to create a delay in my VHDL code because I need to hold
an external clock low for a specified amount of time. I understand
that I have to implement this using clock division and counters since
the wait instruction doesn't synthesize. However, I am unsure of
exactly how to do this.

If I use the board clock, will it run at 50Mhz as specified in the
manual or will it run at the "maximum operating frequency" as specified
in the synthesis report? This is necessary to know in order to know
how much to divide the clock by.

Thank you very much for your help...

Reply With Quote
  #2 (permalink)  
Old 11-23-2006, 03:57 AM
Mark McDougall
Guest
 
Posts: n/a
Default Re: Creating a delay with VHDL without using wait (n00b)

[email protected] wrote:

> If I use the board clock, will it run at 50Mhz as specified in the
> manual or will it run at the "maximum operating frequency" as specified
> in the synthesis report? This is necessary to know in order to know
> how much to divide the clock by.


A 50MHz clock source will run at 50MHz.

The maximum operating frequency is the maximum frequency at which your
design will theoretically run in that piece of silicon.

You need a counter to divide down your clock. For a fully synchronous
design, you will actually be creating a 'clock enable' rather than a
clock signal - there's a difference, and it'll only be active for 1
50MHz period, not 50% duty cycle.

If your counter is too large (i.e. you need to wait a long time) you may
need to pipeline it to speed up your design.

Regards,

--
Mark McDougall, Engineer
Virtual Logic Pty Ltd, <http://www.vl.com.au>
21-25 King St, Rockdale, 2216
Ph: +612-9599-3255 Fax: +612-9599-3266
Reply With Quote
  #3 (permalink)  
Old 11-27-2006, 06:43 PM
wallge
Guest
 
Posts: n/a
Default Re: Creating a delay with VHDL without using wait (n00b)

If you are using an altera device,
just instantiate a phased locked loop mega function
via the mega function wizard in quartus II.
The GUI will guide you through the process
you specify input clock speed,
and the number and frequency of output clocks.
After you're done running through the wizard,
simply instantiate the PLL component in your VHDL
design and connect clock signals to it as appropriate.

If you are using xilinx, the tool for generating useful components
is called core-gen, and has similar functionality to the altera tool.



[email protected] wrote:
> Let me begin by saying that I am new to VHDL.
>
> I would like to create a delay in my VHDL code because I need to hold
> an external clock low for a specified amount of time. I understand
> that I have to implement this using clock division and counters since
> the wait instruction doesn't synthesize. However, I am unsure of
> exactly how to do this.
>
> If I use the board clock, will it run at 50Mhz as specified in the
> manual or will it run at the "maximum operating frequency" as specified
> in the synthesis report? This is necessary to know in order to know
> how much to divide the clock by.
>
> Thank you very much for your help...


Reply With Quote
  #4 (permalink)  
Old 04-05-2010, 11:30 PM
Junior Member
 
Join Date: Apr 2010
Posts: 1
Default

Sorry for digging up an old topic but it was a Google output!

wallge, could you please specify where exactly I may find that PLL mega function, because I didn't find it?! Perhaps things have changed in Quartus in the past few years, and it is located somewhere else.

Thank you in advance!

Quote:
Originally Posted by wallge View Post
If you are using an altera device,
just instantiate a phased locked loop mega function
via the mega function wizard in quartus II.
Reply With Quote
Reply

Bookmarks

Thread Tools
Display Modes

Posting Rules
You may not post new threads
You may not post replies
You may not post attachments
You may not edit your posts

BB code is On
Smilies are On
[IMG] code is On
HTML code is Off
Trackbacks are On
Pingbacks are On
Refbacks are On


Similar Threads
Thread Thread Starter Forum Replies Last Post
VHDL--usage of WAIT statement in PROCESS anil VHDL 1 05-15-2006 10:28 AM
Creating Variable Delay for output signals in an XCV1000 John D. Davis FPGA 4 08-09-2005 12:36 AM
VHDL Wait-Statement after Synthese Roman VHDL 1 10-28-2004 05:01 PM
Xilinx ISE WebPack 5.2 & VHDL : wait synthesis max FPGA 2 08-08-2003 05:01 AM


All times are GMT +1. The time now is 07:32 AM.


Powered by vBulletin® Version 3.8.0
Copyright ©2000 - 2020, Jelsoft Enterprises Ltd.
Search Engine Friendly URLs by vBSEO 3.2.0
Copyright 2008 @ FPGA Central. All rights reserved