FPGA Central

Hi

I have problem when I try to COMPILE / SYNTHESIZE bunch of VHDL source
files.

VHDL source files have hierarchical structure.
For example, top module calls sub-module using LIBRARY declaration.

--------------------------------------------------------------------------------------------
--- As an example
--- Name ls sub-module component : module_network
--- Name of LIBRARY of "module_network" : module_networklib
--- module_network_pkg : definition of component "module_network
LIBRARY module_networklib;
USE module_networklib.module_network_pkg.ALL;
--------------------------------------------------------------------------------------------

Problem is that

When I try to synthesize the top module (in Xilinx ISE), the tool
responds with error message
"Library module_networklib not found"

This is expected, since I do not have "compiled library".

How can we create "compiled library" for sub-modules ?
Can we synthesize the top module, without having "compiled library"?

Thank you in advance for someone, who has this experience.

Pasacco wrote:

> "Library module_networklib not found"
> This is expected, since I do not have "compiled library".
> How can we create "compiled library" for sub-modules ?

Compile the sub-module before any
modules that instance it.
For most synthesis tools this means
to order the file list correctly
and name the top entity correctly.

-- Mike Treseler

On 23 apr, 16:43, Mike Treseler <[email protected]> wrote:
> Pasacco wrote:
> > "Library module_networklib not found"
> > This is expected, since I do not have "compiled library".
> > How can we create "compiled library" for sub-modules ?
>
> Compile the sub-module before any
> modules that instance it.
> For most synthesis tools this means
> to order the file list correctly
> and name the top entity correctly.
>
> -- Mike Treseler

> Compile the sub-module before any
> modules that instance it.
> For most synthesis tools this means
> to order the file list correctly
> and name the top entity correctly.

Does 'compile' mean by 'synthesis' (for example xilinx ISE or
Synplify) ?
Thank you for the comment

Pasacco wrote:
>> Compile the sub-module before any
>> modules that instance it.
>> For most synthesis tools this means
>> to order the file list correctly
>> and name the top entity correctly.
>
> Does 'compile' mean by 'synthesis'

Named libraries are a significant complication
for simulation and synthesis.
Consider using the default "work"
library for your entire design.

-- LIBRARY module_networklib;
-- USE module_networklib.module_network_pkg.ALL;
use work.module_network_pkg.ALL;

-- Mike Treseler

Pasacco wrote:
> Hi
>
> I have problem when I try to COMPILE / SYNTHESIZE bunch of VHDL source
> files.
>
> ...
> Problem is that
>
> When I try to synthesize the top module (in Xilinx ISE), the tool
> responds with error message
> "Library module_networklib not found"
>
> This is expected, since I do not have "compiled library".
>
> How can we create "compiled library" for sub-modules ?
> Can we synthesize the top module, without having "compiled library"?

You are using the ISE GUI? In ISE 8 or 9?

Click on the "Libraries" tab of the main window. Right click and select
"New Source". Select "VHDL Library" and enter the name for the library.
Click ok to create the library. Now right click on the library name in
the window and select "Add Source". Add the VHDL source code. Your
project should now be able to use the libraries.

Now the synthesis is okay.
Thank you very much.

Hi

Thank you for your help.
Now the library mapping is working, in Xilinx ISE (8.2.3) GUI.
But I am not able to find a way to do followings in "command line" (in
Linux)

--------------------------------
(1) New Source -> VHDL Library
(2) Add Source -> lots of VHDL files
--------------------------------

In MODELSIM, this was possible with "vlib -> vmap -> vcom".

I tried to find in "System development guide" and "Synthesis
Verification guide", with no luck.
Could anyone help me with "How to do library mapping" in "command
line"?