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  #1 (permalink)  
Old 11-16-2006, 02:01 AM
nfirtaps
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Posts: n/a
Default conv_integer simulation whining in ISE

I have a circular buffer so my read and write index pointers need to
wrap around to the first index in the circular buffer when incremented
past the last index in the circular buffer. In order to index my
circular buffer I do

circular_buffer(conv_integer(write_index)) <= write_data;
write_index <= write_index + 1;

or

read_data <= circular_buffer(conv_integer(read_index));
read_index <= read_index + 1;

This synthesizes fine but I want read_index and write_index to be in a
modulo ring and wrap around when incremented. The simulator (ISE
Simulator Lite) complains about this treatment. It says Index 16 out
of bound 15 downto 0. I have my read and write indexes as
std_logic_vector(15 downto 0).

How do I work around this?

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  #2 (permalink)  
Old 11-16-2006, 03:38 AM
Ray Andraka
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Posts: n/a
Default Re: conv_integer simulation whining in ISE

nfirtaps wrote:

> I have a circular buffer so my read and write index pointers need to
> wrap around to the first index in the circular buffer when incremented
> past the last index in the circular buffer. In order to index my
> circular buffer I do
>
> circular_buffer(conv_integer(write_index)) <= write_data;
> write_index <= write_index + 1;
>
> or
>
> read_data <= circular_buffer(conv_integer(read_index));
> read_index <= read_index + 1;
>
> This synthesizes fine but I want read_index and write_index to be in a
> modulo ring and wrap around when incremented. The simulator (ISE
> Simulator Lite) complains about this treatment. It says Index 16 out
> of bound 15 downto 0. I have my read and write indexes as
> std_logic_vector(15 downto 0).
>
> How do I work around this?
>


First, use ieee.numeric_std rather than std_logic.unsigned.
ieee.numeric_std is a real standard, unlike the std_logic libraries
which are vendor specific. Numeric_std also uses the same library for
signed and unsigned, so there are no library function name issues that
would otherwise have to be resolved with extensions.

Then:

circular_buffer(to_integer(unsigned(write_index))) <= write_data;
write_index <= (write_index + 1) mod 2**write_index_bits;

mod is synthesizable as long as the modulo is a constant and is an
integer power of 2.
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  #3 (permalink)  
Old 11-16-2006, 04:14 AM
Mike Treseler
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Posts: n/a
Default Re: conv_integer simulation whining in ISE

nfirtaps wrote:
> I have a circular buffer so my read and write index pointers need to
> wrap around to the first index in the circular buffer when incremented
> past the last index in the circular buffer.
> How do I work around this?


Unsigned type can be used inside the process
to roll over as you wish with std_logic_vecotor
type on the ports:

subtype ptr_type is unsigned(add_length-1 downto 0);
-- unsigned wraps
signal pop_head_ptr : ptr_type; -- both _ptr must init same
signal push_tail_ptr : ptr_type;
-- each counts up appropriate cycles

see sync_fifo.vhd here for details:

http://home.comcast.net/~mike_treseler/
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  #4 (permalink)  
Old 11-16-2006, 03:36 PM
Andy
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Posts: n/a
Default Re: conv_integer simulation whining in ISE

Or we can dispense with the vector/integer conversions, and use integer
signals to begin with.

Note that integer math does not roll over automatically, you have to
tell it what you want it to do (mod operator).

constant ndx_size : integer := 8;
subtype ndx_t is integer range 0 to 2**ndx_size - 1;
type buffer_t is array (ndx_t) of std_logic_vector(data_size - 1 downto
0);
signal circular_buffer : buffer_t;
signal rd_ndx, wr_ndx : ndx_t;
....

circular_buffer(wr_ndx) <= write_data;
wr_ndx <= (wr_ndx + 1) mod ndx_t'high;
....
read_data<= circular_buffer(rd_ndx);
rd_ndx <= (rd_ndx + 1) mod ndx_t'high;

And even with the extra mod operations, the integer signals will
simulate _much_ faster.

Andy

Mike Treseler wrote:
> nfirtaps wrote:
> > I have a circular buffer so my read and write index pointers need to
> > wrap around to the first index in the circular buffer when incremented
> > past the last index in the circular buffer.
> > How do I work around this?

>
> Unsigned type can be used inside the process
> to roll over as you wish with std_logic_vecotor
> type on the ports:
>
> subtype ptr_type is unsigned(add_length-1 downto 0);
> -- unsigned wraps
> signal pop_head_ptr : ptr_type; -- both _ptr must init same
> signal push_tail_ptr : ptr_type;
> -- each counts up appropriate cycles
>
> see sync_fifo.vhd here for details:
>
> http://home.comcast.net/~mike_treseler/


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  #5 (permalink)  
Old 11-16-2006, 06:26 PM
nfirtaps
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Posts: n/a
Default Re: conv_integer simulation whining in ISE

Guys, I have tried all 3 of your recommendations to no avail. Let me
show you what I have exactly, here is an example of what Mike
Tresseler recommended. The other two methods have the same result.
Thus, I must have something logically wrong. Here I am using
unsigned's. ISE is very picky what type I index the circular buffer
with.

constant index_size : integer := 16;
subtype index is unsigned(index_size-1 downto 0);
type memory_type is array(index_size-1 downto 0) of
std_logic_vector(index_size-1 downto 0);

signal circ_buff : memory_type;
signal write_index : index;
signal read_index : index;

.....
-- in a process on the rising edge of a clock ....
circ_buff(conv_integer(write_index)) <= ddc_data;
write_index <= write_index+1;
.....
-- in a process on the rising edge of a clock ....
data_out <= circ_buff(conv_integer(read_index));
read_index <= read_index+1;

The simulator says the following on all 3 methods :

Index 16 out of bound 15 downto 0.



Andy wrote:
> Or we can dispense with the vector/integer conversions, and use integer
> signals to begin with.
>
> Note that integer math does not roll over automatically, you have to
> tell it what you want it to do (mod operator).
>
> constant ndx_size : integer := 8;
> subtype ndx_t is integer range 0 to 2**ndx_size - 1;
> type buffer_t is array (ndx_t) of std_logic_vector(data_size - 1 downto
> 0);
> signal circular_buffer : buffer_t;
> signal rd_ndx, wr_ndx : ndx_t;
> ...
>
> circular_buffer(wr_ndx) <= write_data;
> wr_ndx <= (wr_ndx + 1) mod ndx_t'high;
> ...
> read_data<= circular_buffer(rd_ndx);
> rd_ndx <= (rd_ndx + 1) mod ndx_t'high;
>
> And even with the extra mod operations, the integer signals will
> simulate _much_ faster.
>
> Andy
>
> Mike Treseler wrote:
> > nfirtaps wrote:
> > > I have a circular buffer so my read and write index pointers need to
> > > wrap around to the first index in the circular buffer when incremented
> > > past the last index in the circular buffer.
> > > How do I work around this?

> >
> > Unsigned type can be used inside the process
> > to roll over as you wish with std_logic_vecotor
> > type on the ports:
> >
> > subtype ptr_type is unsigned(add_length-1 downto 0);
> > -- unsigned wraps
> > signal pop_head_ptr : ptr_type; -- both _ptr must init same
> > signal push_tail_ptr : ptr_type;
> > -- each counts up appropriate cycles
> >
> > see sync_fifo.vhd here for details:
> >
> > http://home.comcast.net/~mike_treseler/


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  #6 (permalink)  
Old 11-16-2006, 09:19 PM
Andy
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Posts: n/a
Default Re: conv_integer simulation whining in ISE

If index has index_size bits, then the buffer needs (2**index_size)
elements (2**index_size -1 downto 0). You are overflowing the index to
the buffer, not the index counts themselves.

Andy


nfirtaps wrote:
> Guys, I have tried all 3 of your recommendations to no avail. Let me
> show you what I have exactly, here is an example of what Mike
> Tresseler recommended. The other two methods have the same result.
> Thus, I must have something logically wrong. Here I am using
> unsigned's. ISE is very picky what type I index the circular buffer
> with.
>
> constant index_size : integer := 16;
> subtype index is unsigned(index_size-1 downto 0);
> type memory_type is array(index_size-1 downto 0) of
> std_logic_vector(index_size-1 downto 0);
>
> signal circ_buff : memory_type;
> signal write_index : index;
> signal read_index : index;
>
> ....
> -- in a process on the rising edge of a clock ....
> circ_buff(conv_integer(write_index)) <= ddc_data;
> write_index <= write_index+1;
> ....
> -- in a process on the rising edge of a clock ....
> data_out <= circ_buff(conv_integer(read_index));
> read_index <= read_index+1;
>
> The simulator says the following on all 3 methods :
>
> Index 16 out of bound 15 downto 0.
>
>
>
> Andy wrote:
> > Or we can dispense with the vector/integer conversions, and use integer
> > signals to begin with.
> >
> > Note that integer math does not roll over automatically, you have to
> > tell it what you want it to do (mod operator).
> >
> > constant ndx_size : integer := 8;
> > subtype ndx_t is integer range 0 to 2**ndx_size - 1;
> > type buffer_t is array (ndx_t) of std_logic_vector(data_size - 1 downto
> > 0);
> > signal circular_buffer : buffer_t;
> > signal rd_ndx, wr_ndx : ndx_t;
> > ...
> >
> > circular_buffer(wr_ndx) <= write_data;
> > wr_ndx <= (wr_ndx + 1) mod ndx_t'high;
> > ...
> > read_data<= circular_buffer(rd_ndx);
> > rd_ndx <= (rd_ndx + 1) mod ndx_t'high;
> >
> > And even with the extra mod operations, the integer signals will
> > simulate _much_ faster.
> >
> > Andy
> >
> > Mike Treseler wrote:
> > > nfirtaps wrote:
> > > > I have a circular buffer so my read and write index pointers need to
> > > > wrap around to the first index in the circular buffer when incremented
> > > > past the last index in the circular buffer.
> > > > How do I work around this?
> > >
> > > Unsigned type can be used inside the process
> > > to roll over as you wish with std_logic_vecotor
> > > type on the ports:
> > >
> > > subtype ptr_type is unsigned(add_length-1 downto 0);
> > > -- unsigned wraps
> > > signal pop_head_ptr : ptr_type; -- both _ptr must init same
> > > signal push_tail_ptr : ptr_type;
> > > -- each counts up appropriate cycles
> > >
> > > see sync_fifo.vhd here for details:
> > >
> > > http://home.comcast.net/~mike_treseler/


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  #7 (permalink)  
Old 11-16-2006, 10:03 PM
nfirtaps
Guest
 
Posts: n/a
Default Re: conv_integer simulation whining in ISE

Ah, for some reason I thought at array (array(n downto 0)) has 2**n-1
elements, oops. Thanks a ton for all the replies they helped so much.

Lloyd


Andy wrote:
> If index has index_size bits, then the buffer needs (2**index_size)
> elements (2**index_size -1 downto 0). You are overflowing the index to
> the buffer, not the index counts themselves.
>
> Andy
>
>
> nfirtaps wrote:
> > Guys, I have tried all 3 of your recommendations to no avail. Let me
> > show you what I have exactly, here is an example of what Mike
> > Tresseler recommended. The other two methods have the same result.
> > Thus, I must have something logically wrong. Here I am using
> > unsigned's. ISE is very picky what type I index the circular buffer
> > with.
> >
> > constant index_size : integer := 16;
> > subtype index is unsigned(index_size-1 downto 0);
> > type memory_type is array(index_size-1 downto 0) of
> > std_logic_vector(index_size-1 downto 0);
> >
> > signal circ_buff : memory_type;
> > signal write_index : index;
> > signal read_index : index;
> >
> > ....
> > -- in a process on the rising edge of a clock ....
> > circ_buff(conv_integer(write_index)) <= ddc_data;
> > write_index <= write_index+1;
> > ....
> > -- in a process on the rising edge of a clock ....
> > data_out <= circ_buff(conv_integer(read_index));
> > read_index <= read_index+1;
> >
> > The simulator says the following on all 3 methods :
> >
> > Index 16 out of bound 15 downto 0.
> >
> >
> >
> > Andy wrote:
> > > Or we can dispense with the vector/integer conversions, and use integer
> > > signals to begin with.
> > >
> > > Note that integer math does not roll over automatically, you have to
> > > tell it what you want it to do (mod operator).
> > >
> > > constant ndx_size : integer := 8;
> > > subtype ndx_t is integer range 0 to 2**ndx_size - 1;
> > > type buffer_t is array (ndx_t) of std_logic_vector(data_size - 1 downto
> > > 0);
> > > signal circular_buffer : buffer_t;
> > > signal rd_ndx, wr_ndx : ndx_t;
> > > ...
> > >
> > > circular_buffer(wr_ndx) <= write_data;
> > > wr_ndx <= (wr_ndx + 1) mod ndx_t'high;
> > > ...
> > > read_data<= circular_buffer(rd_ndx);
> > > rd_ndx <= (rd_ndx + 1) mod ndx_t'high;
> > >
> > > And even with the extra mod operations, the integer signals will
> > > simulate _much_ faster.
> > >
> > > Andy
> > >
> > > Mike Treseler wrote:
> > > > nfirtaps wrote:
> > > > > I have a circular buffer so my read and write index pointers need to
> > > > > wrap around to the first index in the circular buffer when incremented
> > > > > past the last index in the circular buffer.
> > > > > How do I work around this?
> > > >
> > > > Unsigned type can be used inside the process
> > > > to roll over as you wish with std_logic_vecotor
> > > > type on the ports:
> > > >
> > > > subtype ptr_type is unsigned(add_length-1 downto 0);
> > > > -- unsigned wraps
> > > > signal pop_head_ptr : ptr_type; -- both _ptr must init same
> > > > signal push_tail_ptr : ptr_type;
> > > > -- each counts up appropriate cycles
> > > >
> > > > see sync_fifo.vhd here for details:
> > > >
> > > > http://home.comcast.net/~mike_treseler/


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  #8 (permalink)  
Old 11-16-2006, 10:03 PM
nfirtaps
Guest
 
Posts: n/a
Default Re: conv_integer simulation whining in ISE

Ah, for some reason I thought at array (array(n downto 0)) has 2**n-1
elements, oops. Thanks a ton for all the replies they helped so much.

Lloyd


Andy wrote:
> If index has index_size bits, then the buffer needs (2**index_size)
> elements (2**index_size -1 downto 0). You are overflowing the index to
> the buffer, not the index counts themselves.
>
> Andy
>
>
> nfirtaps wrote:
> > Guys, I have tried all 3 of your recommendations to no avail. Let me
> > show you what I have exactly, here is an example of what Mike
> > Tresseler recommended. The other two methods have the same result.
> > Thus, I must have something logically wrong. Here I am using
> > unsigned's. ISE is very picky what type I index the circular buffer
> > with.
> >
> > constant index_size : integer := 16;
> > subtype index is unsigned(index_size-1 downto 0);
> > type memory_type is array(index_size-1 downto 0) of
> > std_logic_vector(index_size-1 downto 0);
> >
> > signal circ_buff : memory_type;
> > signal write_index : index;
> > signal read_index : index;
> >
> > ....
> > -- in a process on the rising edge of a clock ....
> > circ_buff(conv_integer(write_index)) <= ddc_data;
> > write_index <= write_index+1;
> > ....
> > -- in a process on the rising edge of a clock ....
> > data_out <= circ_buff(conv_integer(read_index));
> > read_index <= read_index+1;
> >
> > The simulator says the following on all 3 methods :
> >
> > Index 16 out of bound 15 downto 0.
> >
> >
> >
> > Andy wrote:
> > > Or we can dispense with the vector/integer conversions, and use integer
> > > signals to begin with.
> > >
> > > Note that integer math does not roll over automatically, you have to
> > > tell it what you want it to do (mod operator).
> > >
> > > constant ndx_size : integer := 8;
> > > subtype ndx_t is integer range 0 to 2**ndx_size - 1;
> > > type buffer_t is array (ndx_t) of std_logic_vector(data_size - 1 downto
> > > 0);
> > > signal circular_buffer : buffer_t;
> > > signal rd_ndx, wr_ndx : ndx_t;
> > > ...
> > >
> > > circular_buffer(wr_ndx) <= write_data;
> > > wr_ndx <= (wr_ndx + 1) mod ndx_t'high;
> > > ...
> > > read_data<= circular_buffer(rd_ndx);
> > > rd_ndx <= (rd_ndx + 1) mod ndx_t'high;
> > >
> > > And even with the extra mod operations, the integer signals will
> > > simulate _much_ faster.
> > >
> > > Andy
> > >
> > > Mike Treseler wrote:
> > > > nfirtaps wrote:
> > > > > I have a circular buffer so my read and write index pointers need to
> > > > > wrap around to the first index in the circular buffer when incremented
> > > > > past the last index in the circular buffer.
> > > > > How do I work around this?
> > > >
> > > > Unsigned type can be used inside the process
> > > > to roll over as you wish with std_logic_vecotor
> > > > type on the ports:
> > > >
> > > > subtype ptr_type is unsigned(add_length-1 downto 0);
> > > > -- unsigned wraps
> > > > signal pop_head_ptr : ptr_type; -- both _ptr must init same
> > > > signal push_tail_ptr : ptr_type;
> > > > -- each counts up appropriate cycles
> > > >
> > > > see sync_fifo.vhd here for details:
> > > >
> > > > http://home.comcast.net/~mike_treseler/


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  #9 (permalink)  
Old 11-17-2006, 02:37 AM
Ray Andraka
Guest
 
Posts: n/a
Default Re: conv_integer simulation whining in ISE

nfirtaps wrote:

> Guys, I have tried all 3 of your recommendations to no avail. Let me
> show you what I have exactly, here is an example of what Mike
> Tresseler recommended. The other two methods have the same result.
> Thus, I must have something logically wrong. Here I am using
> unsigned's. ISE is very picky what type I index the circular buffer
> with.
>
> constant index_size : integer := 16;
> subtype index is unsigned(index_size-1 downto 0);
> type memory_type is array(index_size-1 downto 0) of
> std_logic_vector(index_size-1 downto 0);
>
> signal circ_buff : memory_type;
> signal write_index : index;
> signal read_index : index;
>
> ....
> -- in a process on the rising edge of a clock ....
> circ_buff(conv_integer(write_index)) <= ddc_data;
> write_index <= write_index+1;
> ....
> -- in a process on the rising edge of a clock ....
> data_out <= circ_buff(conv_integer(read_index));
> read_index <= read_index+1;
>
> The simulator says the following on all 3 methods :
>
> Index 16 out of bound 15 downto 0.
>


You need to use the mod operator or some conditional execution to keep
the index within the range 0 to 15.

read_index <= (read_index+1) mod 16;

will do it, as will:

read_index <= read_index+1;
if read_index > 15 then
read_index <= read_index - 16;

or
if read_index > 15 then
read_index <= 0;
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