Compare pairs of bits between two slv's ?
I've been puzzling how I can write concise vhdl that will basically set a
bit if any pair of bits in two slv's are both hi ? A sort of pseudo code for what I want to do is as follows mask : std_logic_vector(7 downto 0) ; trig : std_logic_vector(7 downto 0) ; set : std_logic; set <= '0' ; for i in 0 to 7 If mask(i) AND trig(i) = '1' set <= '1' ; end if ; end for ; In english, if any pair of bits in the two slv's are both hi, the set will be set to one, else zero I thought about using ForGenerate, but I'm puzzled how to apply for this case ? Regards Tony 
Re: Compare pairs of bits between two slv's ?
S1 <= '0' when (Mask and Trig) = 0 else '1';

Re: Compare pairs of bits between two slv's ?
This is why we are thinking of putting vector reduction into VHDL. Try this: set := or_reduce (mask and trig); You will find a copy of "or_reduce" at: http://www.vhdl.org/vhdlsynth/ This is functionality we also plan to add in 1164 as well. Tony Benham wrote: > I've been puzzling how I can write concise vhdl that will basically set a > bit if any pair of bits in two slv's are both hi ? > A sort of pseudo code for what I want to do is as follows > mask : std_logic_vector(7 downto 0) ; > trig : std_logic_vector(7 downto 0) ; > set : std_logic; > > set <= '0' ; > for i in 0 to 7 > If mask(i) AND trig(i) = '1' > set <= '1' ; > end if ; > end for ; > > In english, if any pair of bits in the two slv's are both hi, the set will > be set to one, else zero > > I thought about using ForGenerate, but I'm puzzled how to apply for this > case ? > > Regards > Tony > >  NAME: David W. Bishop INTERNET: [email protected] ( \ ) US MAIL: Hilton NY A Long time ago, \__\/ PHYSICAL: 43:17:17N 77:47:37W 281' In a Galaxy far, far away...   For Supernova info: http://www.RochesterAstronomy.org/snimages/   For VHDL/Synthesis info: http://www.vhdl.org/vhdlsynth _/___\_ All standard disclaimers apply. [_______] 
Re: Compare pairs of bits between two slv's ?
I've just reading an answer to my qustion here
http://www.eda.org/comp.lang.vhdl/FAQ1.html and encountered Reduction section.  this concurrent assignment performs an "or"  reduction on "a_vec" a <= '0' when (a_vec = (a_vec'range => '0')) else '1';  while this calculates an "and" reduction a <= '1' when (a_vec = (a_vec'range => '1')) else '0'; Read there about reducing vectors containing 'X' values. 
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