FPGA Central - World's 1st FPGA / CPLD Portal

FPGA Central

World's 1st FPGA Portal


Go Back   FPGA Groups > NewsGroup > VHDL

VHDL comp.lang.vhdl newsgroup / Usenet

LinkBack Thread Tools Display Modes
  #1 (permalink)  
Old 09-23-2006, 01:10 AM
Jim Lewis
Posts: n/a
Default Call for Participation Accellera VHDL Verification Features

If you have strong verification skills and have used
a language such as SystemVerilog, e, Vera, or SystemC
for verification and would like to be able to use
VHDL, you should be participating in the Accellera
VHDL enhancments effort.

Some of the tasks on our list are adding OO, interfaces,
constrained random, functional coverage, verification
data structures, ...

You do not need to be an Accellera member to participate.
Go to the webpage

Under join here, select the appropriate "click here"
link (Accellera member vs. non-member).

Non-Accellera members fill in your name and information
and send the request to Lynn Horobin, Administration & Marketing.
In the big text box, ask to join Accellera VHDL TSC,
VHDL Extensions subcommittee, and VHDL Requirements subcommittee.

Note that most decisions are made by consensus of all
participants. Only contentious items are decided by a
member based vote. In the last revision, I think there
were only 3 of over 100 items resolved this way.

Of course for those of you who belong to companies with
sufficient resources, membership in Accellera will help
fund the effort (mainly LRM editing task) and is greatly

Best Regards,
Jim Lewis
VHDL and VHDL Standards Evangalist

~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ~~~~~~~~~~~
Jim Lewis
Director of Training mailto:[email protected]
SynthWorks Design Inc. http://www.SynthWorks.com

Expert VHDL Training for Hardware Design and Verification
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ~~~~~~~~~~~
Reply With Quote
  #2 (permalink)  
Old 10-01-2006, 08:54 AM
Posts: n/a
Default Re: Call for Participation Accellera VHDL Verification Features

I subscribed/sent an email via that page showing interest, didn't
hear back anything from anyone from the commitee? Is there another
channel that I should pursue?


Reply With Quote
  #3 (permalink)  
Old 10-17-2006, 03:41 PM
Chris Foster
Posts: n/a
Default Re: Call for Participation Accellera VHDL Verification Features

Jim Lewis <[email protected]> wrote in news:12h8ur17fq16r39

> http://www.accellera.org/activities/vhdl/

I signeed up as you asked at MAPLD. We will se how far I get without
your assistance

Chris Foster

Posted via a free Usenet account from http://www.teranews.com

Reply With Quote


Thread Tools
Display Modes

Posting Rules
You may not post new threads
You may not post replies
You may not post attachments
You may not edit your posts

BB code is On
Smilies are On
[IMG] code is On
HTML code is Off
Trackbacks are On
Pingbacks are On
Refbacks are On

Similar Threads
Thread Thread Starter Forum Replies Last Post
FPL 2008 : Call for Participation David Thomas FPGA 0 07-17-2008 02:14 AM
Breaking News ... Accellera Verification Working Group Forming [email protected] Verilog 8 05-21-2008 09:58 PM
Breaking News ... Accellera Verification Working Group Forming HairyTheASICG[email protected] FPGA 5 05-12-2008 06:04 PM
Call for Participation Accellera VHDL Verification Features Jim Lewis FPGA 0 09-23-2006 01:12 AM
Accellera, OVL, and VHDL? geocon VHDL 2 10-06-2005 07:54 PM

All times are GMT +1. The time now is 09:18 AM.

Powered by vBulletin® Version 3.8.0
Copyright ©2000 - 2020, Jelsoft Enterprises Ltd.
Search Engine Friendly URLs by vBSEO 3.2.0
Copyright 2008 @ FPGA Central. All rights reserved