FPGA Central - World's 1st FPGA / CPLD Portal

FPGA Central

World's 1st FPGA Portal


Go Back   FPGA Groups > NewsGroup > VHDL

VHDL comp.lang.vhdl newsgroup / Usenet

LinkBack Thread Tools Display Modes
  #1 (permalink)  
Old 09-13-2003, 04:50 AM
Posts: n/a
Default A bus in a symbol with Viewlogic

I have a problem with adding a bus to a symbol with viewlogic 7.2.
Thank's for your help

Reply With Quote


Thread Tools
Display Modes

Posting Rules
You may not post new threads
You may not post replies
You may not post attachments
You may not edit your posts

BB code is On
Smilies are On
[IMG] code is On
HTML code is Off
Trackbacks are On
Pingbacks are On
Refbacks are On

Similar Threads
Thread Thread Starter Forum Replies Last Post
Any *really old* Viewlogic / Xilinx users around here? :) Peter FPGA 2 07-14-2006 02:52 AM
How crate symbol from VHD? buke2 FPGA 1 08-11-2004 08:43 PM
Adding a bus to a symbol with viewlogic Momo Verilog 0 09-13-2003 04:53 AM
Re: MapLib:93 - Illegal LOC on symbol "clk.PAD" (pad signal=clk) or BUFGP symbol "u1" (output signal=u1), IPAD-IBUFG should only be LOC'd to GCLKIOB site." Sandeep Kulkarni FPGA 0 07-02-2003 11:35 AM

All times are GMT +1. The time now is 03:20 AM.

Powered by vBulletin® Version 3.8.0
Copyright ©2000 - 2020, Jelsoft Enterprises Ltd.
Search Engine Friendly URLs by vBSEO 3.2.0
Copyright 2008 @ FPGA Central. All rights reserved