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Old 09-22-2003, 08:45 AM
Max
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Default buffer port

I have this files:

------ main.vhd---------------
entity main is
Port ( sig : buffer std_logic);
end main;

architecture Behavioral of main is

component a is
Port ( siga : in std_logic);
end component;
component b is
Port ( sigb : out std_logic);
end component;

begin
aa: component a
Port map( siga => sig);
bb: component b
Port map ( sigb => sig); -- here is the error
end Behavioral;
--
----------- a.vhd --------------------
entity a is
Port ( siga : in std_logic);
end a;
architecture Behavioral of a is
begin

end Behavioral;
--
----------- b.vhd --------------------
entity b is
Port ( sigb : out std_logic);
end b;
architecture Behavioral of b is
begin
sigb <= '1';
end Behavioral;
--

I obtain the following error in synthesis:
ERROR:HDLParsers:1411 - main.vhd Line XX. Parameter sig of mode buffer
can not be associated with a formal port of mode out.

Buffer port is the same of out port, but can be read from within the
entity, isn't it?
So why occurs this error.

thanks
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  #2 (permalink)  
Old 09-22-2003, 11:41 AM
Egbert Molenkamp
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Posts: n/a
Default Re: buffer port

Max,

You will find your answer in the faq
http://www.vhdl.org/vi/comp.lang.vhd...l#buffer_ports

Egbert Molenkamp


"Max" <[email protected]> schreef in bericht
news:[email protected] om...
> I have this files:
>
> ------ main.vhd---------------
> entity main is
> Port ( sig : buffer std_logic);
> end main;
>
> architecture Behavioral of main is
>
> component a is
> Port ( siga : in std_logic);
> end component;
> component b is
> Port ( sigb : out std_logic);
> end component;
>
> begin
> aa: component a
> Port map( siga => sig);
> bb: component b
> Port map ( sigb => sig); -- here is the error
> end Behavioral;
> --
> ----------- a.vhd --------------------
> entity a is
> Port ( siga : in std_logic);
> end a;
> architecture Behavioral of a is
> begin
>
> end Behavioral;
> --
> ----------- b.vhd --------------------
> entity b is
> Port ( sigb : out std_logic);
> end b;
> architecture Behavioral of b is
> begin
> sigb <= '1';
> end Behavioral;
> --
>
> I obtain the following error in synthesis:
> ERROR:HDLParsers:1411 - main.vhd Line XX. Parameter sig of mode buffer
> can not be associated with a formal port of mode out.
>
> Buffer port is the same of out port, but can be read from within the
> entity, isn't it?
> So why occurs this error.
>
> thanks



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