FPGA Central

Hi,

I always run into the issue of having counters
or adders where I don't want the resulting value
to exceed a certain threshold.

Here's an example but maybe not the best solution
in terms of synthesis:

signal count : std_logic_vector(7 downto 0);
signal addval : std_logic_vector(7 downto 0);
constant rollover : natural := 255;
begin
process(count,addval)
begin
if( count + addval > rollover ) then
count <= rollover;
else
count <= count+addval;
end if;
end process;

Rollover can sometimes be a signal. And usually I
will use clocked processes.

Does the above code infer two adders and a comparator?

So what would be the best solution in terms of
synthesis? I work with Xilinx ISE and Virtex V4s.


Brad Smallridge
AiVision

Brad Smallridge wrote:
> Hi,
>
> I always run into the issue of having counters
> or adders where I don't want the resulting value
> to exceed a certain threshold.
>
> Here's an example but maybe not the best solution
> in terms of synthesis:
>
> signal count : std_logic_vector(7 downto 0);
> signal addval : std_logic_vector(7 downto 0);
> constant rollover : natural := 255;
> begin
> process(count,addval)
> begin
> if( count + addval > rollover ) then
> count <= rollover;
> else
> count <= count+addval;
> end if;
> end process;
>
> Rollover can sometimes be a signal. And usually I
> will use clocked processes.
>
> Does the above code infer two adders and a comparator?
>
> So what would be the best solution in terms of
> synthesis? I work with Xilinx ISE and Virtex V4s.
>
>
> Brad Smallridge
> AiVision
>

I think the logic is a little off here--it seems like 'count' gets stuck
at 'rollover' and then never changes. That is, if addval=5,
rollover=23, then count=0,5,10,15,20,23,23,23,23,23,....
-Kevin

On Wed, 07 May 2008 15:51:02 -0600, Kevin Neilson
<[email protected]> wrote:

>Brad Smallridge wrote:
>> Hi,
>>
>> I always run into the issue of having counters
>> or adders where I don't want the resulting value
>> to exceed a certain threshold.
>>
>> Here's an example but maybe not the best solution
>> in terms of synthesis:
>>
>> signal count : std_logic_vector(7 downto 0);
>> signal addval : std_logic_vector(7 downto 0);
>> constant rollover : natural := 255;
>> begin
>> process(count,addval)
>> begin
>> if( count + addval > rollover ) then
>> count <= rollover;
>> else
>> count <= count+addval;
>> end if;
>> end process;
>>
>> Rollover can sometimes be a signal. And usually I
>> will use clocked processes.
>>
>> Does the above code infer two adders and a comparator?

If it does, shoot the synthesis tool.

Or move count+addval outside the process to save an adder.

sum <= count + addval; -- could pipeline for speed, see below

process( ...
if sum > rollover then
-- no need to bracket the expression - this isn't c++

>> So what would be the best solution in terms of
>> synthesis? I work with Xilinx ISE and Virtex V4s.

I see no general way to avoid the comparator, though in your example you
could simply extend sum to 9 bits and test the MSB.

library IEEE;
use IEEE.numeric_std.all;

signal count : unsigned(7 downto 0); -- NOT std_logic_vector!
signal addval : unsigned(7 downto 0);
signal sum : unsigned(8 downto 0);

constant rollover : natural := 255;

begin

--sum <= count + addval; -- uncomment for slow original semantics

process(clk)
begin
if rising_edge(clk) then
sum <= count + addval;
-- introduces a cycle delay; but faster clock rate possible
-- comment out and uncomment above for original semantics
if sum(sum'high) = '1' then
count <= rollover;
else
count <= sum(count'range);
end if;
end if;
end process;

>
>I think the logic is a little off here--it seems like 'count' gets stuck
>at 'rollover' and then never changes. That is, if addval=5,
>rollover=23, then count=0,5,10,15,20,23,23,23,23,23,....
>-Kevin

That's not necessarily off - quite often, saturating arithmetic is
required. Some mainstream* CPUs offer machine instructions or operating
modes to perform it.

In this example I expect the "count down" or reset clause was omitted
for clarity.

*mainstream if you're into DSP!
- Brian

> process(clk)
> begin
> if rising_edge(clk) then
> sum <= count + addval;
> -- introduces a cycle delay; but faster clock rate possible
> -- comment out and uncomment above for original semantics
> if sum(sum'high) = '1' then
> count <= rollover;
> else
> count <= sum(count'range);
> end if;
> end if;
> end process;

Thanks. I have used this method, with and without clocks.
I have also fudged the init count so that the count maxes
earlier. But then the count is a little hard to read or use
if it connects elsewhere in the system.

> In this example I expect the "count down" or reset clause was omitted
> for clarity.

Yes.

> *mainstream if you're into DSP!

I don't know what *mainstream is. But I have also used the DSP48
to count.

Brad Smallridge
Ai Vision

Brad Smallridge wrote:
>> process(clk)
>> begin
>> if rising_edge(clk) then
>> sum <= count + addval;
>> -- introduces a cycle delay; but faster clock rate possible
>> -- comment out and uncomment above for original semantics
>> if sum(sum'high) = '1' then
>> count <= rollover;
>> else
>> count <= sum(count'range);
>> end if;
>> end if;
>> end process;
>
> Thanks. I have used this method, with and without clocks.
> I have also fudged the init count so that the count maxes
> earlier. But then the count is a little hard to read or use
> if it connects elsewhere in the system.
>
>> In this example I expect the "count down" or reset clause was omitted
>> for clarity.
>
> Yes.
>
>> *mainstream if you're into DSP!
>
> I don't know what *mainstream is. But I have also used the DSP48
> to count.
>
> Brad Smallridge
> Ai Vision
>
>
>
>
>
I haven't used it, but the DSP48E (in the V5) has a built-in comparator
you can use for rollovers. Also, if you don't need all 48 bits, you can
split it into two or four separate counters. -Kevin