FPGA Central

Hello

I need to write a testbench which assigns one value at the rising edge and
another value at the falling edge of the clock.

I tried the code below but the value is always assignd only at the rising
edge. What is my mistake?

Thank you
Sincerely
Lore

....
blabla: process
variable i : integer;
begin
s_clk <= '0';
s_reset <= '0';
s_reset <= '1';

while i<50 loop
s_din <= std_logic_vector(to_unsigned(i,width)); -- integer nach
std_logic vector
s_clk <= '1';
wait for 50 ns;
i:= i + 1;
s_din <= std_logic_vector(to_unsigned(i,width)); -- integer nach
std_logic vector
s_clk <= '0';
wait for 50 ns;
end loop;

end process;
....

"Lore Leunoeg" <[email protected]> wrote in message
news:[email protected]...
> Hello
>
> I need to write a testbench which assigns one value at the rising edge and
> another value at the falling edge of the clock.
>
> I tried the code below but the value is always assignd only at the rising
> edge. What is my mistake?
>
It is assigning at both edges, but you're only seeing it change at the
falling edge (not the rising edge as you state) because you never changed
the value of the variable 'i' prior to the rising edge assignment. I'm
assuming that you want to increment 'i' at both places which means that you
need to add "i:= i + 1;" either prior to the first assignment to s_din (the
one preceding when s_clk gets set to 1) or just prior to the "end loop"
statement. Lastly, you have no initial assignment for the variable 'i'
which is probably a mistake as well.

Kevin Jennings

I think that correctly you need use 2x frequncy.


Lore Leunoeg:
> Hello
>
> I need to write a testbench which assigns one value at the rising edge and
> another value at the falling edge of the clock.
>
> I tried the code below but the value is always assignd only at the rising
> edge. What is my mistake?
>
> Thank you
> Sincerely
> Lore
>
> ...
> blabla: process
> variable i : integer;
> begin
> s_clk <= '0';
> s_reset <= '0';
> s_reset <= '1';
>
> while i<50 loop
> s_din <= std_logic_vector(to_unsigned(i,width)); -- integer nach
> std_logic vector
> s_clk <= '1';
> wait for 50 ns;
> i:= i + 1;
> s_din <= std_logic_vector(to_unsigned(i,width)); -- integer nach
> std_logic vector
> s_clk <= '0';
> wait for 50 ns;
> end loop;
>
> end process;
> ...