FPGA Central

Hi,

what is the difference between the following processes
if I want to use the basic clock and the derived clock for my
simulation with Modelsim?


process(clk)
begin
if clk='1' then
clk2 <= not clk2;
end if;
end process;
-- clk and clk2 are used for simulation
----------------------------------------------

process(clk)
begin
clk1 <= clk;
if clk='1' then
clk2 <= not clk2;
end if;
end process;
-- clk1 and clk2 are used for simulation

Thank you for your help.

Best regards

ALuPin wrote:


> what is the difference between the following processes
> if I want to use the basic clock and the derived clock for my
> simulation with Modelsim?
>
>
> process(clk)
> begin
> if clk='1' then
> clk2 <= not clk2;
> end if;
> end process;
> -- clk and clk2 are used for simulation

clk2 is never reseted - it stays at 'X' forever.

Don't put clk2 into the sensitivity list! You would get an infinite loop.


Better would be - if it matches your desired functionality (I am not
shure what you want!):


process(reset,clk)
begin
if (reset='1') then
clk2<='0';
elsif rising_edge(clk) then
clk2<=NOT(clk2); -- simple clock devider
end if;
end process;


> ----------------------------------------------
>
> process(clk)
> begin
> clk1 <= clk;
> if clk='1' then
> clk2 <= not clk2;
> end if;
> end process;
> -- clk1 and clk2 are used for simulation


For clk1 this is the same as

clk1<=clk;

(no process). clk1 is a simple copy of clk.


clk2 has the same behavior as in the 1st process.


Ralf

"ALuPin" <[email protected]> escribió en el mensaje
news:[email protected] om...
> Hi,
>
> what is the difference between the following processes
> if I want to use the basic clock and the derived clock for my
> simulation with Modelsim?
>

what do you mean by "aligning signals"? what signals are you aligning?
if you have modelsim why dont you just simulate it to see if you get the
correct behaviour? which only you knows, as it cant be "extracted" from
these small pieces of code...

>
> process(clk)
> begin
> if clk='1' then
> clk2 <= not clk2;
> end if;
> end process;
> -- clk and clk2 are used for simulation
> ----------------------------------------------
>

i dont understand what exactly are you trying to do, but it seems like
you're "dividing" the frequency of clk, use a DFF then, a divider is a DFF
with it's "Qn" output conected to it's "D" input, the output of the divider
can be either Q or Qn

process(CLK, RSTn)
begin
if (RSTn = '0') then
Q <= '0';
elsif (rising_edge(CLK)) then
Q <= D;
end if;
end process;

D <= not Q; -- (which of course you could put in the elsif of
the process, by putting Q <= not Q; )



> process(clk)
> begin
> clk1 <= clk;
> if clk='1' then
> clk2 <= not clk2;
> end if;
> end process;
> -- clk1 and clk2 are used for simulation
>
> Thank you for your help.
>
> Best regards

the same as before, you just have

clk1 <= clk;

but again, you'd be better simulating stuff in modelsim to see what fits
your needs better

ALuPin wrote:
> Hi,
>
> what is the difference between the following processes
> if I want to use the basic clock and the derived clock for my
> simulation with Modelsim?
>
>
> process(clk)
> begin
> if clk='1' then
> clk2 <= not clk2;
> end if;
> end process;
> -- clk and clk2 are used for simulation
> ----------------------------------------------
>
> process(clk)
> begin
> clk1 <= clk;
> if clk='1' then
> clk2 <= not clk2;
> end if;
> end process;
> -- clk1 and clk2 are used for simulation
>
> Thank you for your help.
>
> Best regards
Beside that reset behavior already mentioned you will have problems if
you hand over signals from flops clocked by clk to flops clocked by clk2
since clk2 will change 1 delta cycle later than clk and this is enough
to update outputs of flops clocked by clk. You second soultion avoids
this by 'generating' both clocks in the same delta cycle.
HTH

-Eyck