FPGA Central - World's 1st FPGA / CPLD Portal

FPGA Central

World's 1st FPGA Portal

 

Go Back   FPGA Groups > NewsGroup > VHDL

VHDL comp.lang.vhdl newsgroup / Usenet

Reply
 
LinkBack Thread Tools Display Modes
  #1 (permalink)  
Old 11-05-2006, 10:52 PM
Guest
 
Posts: n/a
Default AHDL program: HELP!

I know this is a VHDL group, however, since there is no AHDL group and
I read more than one post in which people talked about using or having
used AHDL I suppose I can find some help in here.
This is the code:

SUBDESIGN FlipD
(
D,LE,CL,PS :INPUT;
Q :OUTPUT;
)

VARIABLE
tmp[1..0] :NODE; %store latches outputs%
en,out :NODE; %Enable of slave latch and master-latch output%
%prep[1..0] :NODE; %Array of preparatory states%

BEGIN

tmp[0]=out; %copies MASTER-output%
tmp[1]=Q; %copies SLAVE-output%
en=!LE; %SLAVE latch-enable (negation of LE)%
prep[]=(PS,CL);

IF(LE==VCC) THEN %Latch-Enable on%

CASE prep[] IS
WHEN b"01"=>% CL activated, out goes to GND%
out=GND;
WHEN b"10"=>%PS activated, out goes to VCC%
out=VCC;
WHEN OTHERS=>%any other combination: transparent latch%
out=D;

END CASE;
END IF;
ELSE
out=tmp[0]; %MASTER-output remains the same%
END IF;

IF(en==VCC) THEN %if slave is enabled%
Q=out; %update output value by copying MASTER output%
ELSE
Q=tmp[1];%SLAVE output remains the same%
END IF;
END;

What I'm trying to do with this code is a D type Flip-Flop. The funny
thing is that if I remove the CASE block (which analices CL and PS
inputs), the thing works just right, but when I try to simulate the
whole program (with CL and PS set in any different values, it doesn't
make a difference) the output gets stucked at VCC forever.
Any ideas?

Reply With Quote
Reply

Bookmarks

Thread Tools
Display Modes

Posting Rules
You may not post new threads
You may not post replies
You may not post attachments
You may not edit your posts

BB code is On
Smilies are On
[IMG] code is On
HTML code is Off
Trackbacks are On
Pingbacks are On
Refbacks are On


Similar Threads
Thread Thread Starter Forum Replies Last Post
Impact won't program XC3S200, does program XC3SD1800A Paul Boven FPGA 2 03-31-2008 11:19 PM
ahdl --> vhdl zlotawy FPGA 1 01-30-2007 11:50 PM
[AHDL] news1.ustronie.pw.edu.pl VHDL 3 05-02-2006 08:47 PM
Need help with AHDL methi VHDL 0 06-22-2005 05:01 PM
Need help with AHDL methi FPGA 0 06-22-2005 04:44 PM


All times are GMT +1. The time now is 02:13 AM.


Powered by vBulletin® Version 3.8.0
Copyright ©2000 - 2020, Jelsoft Enterprises Ltd.
Search Engine Friendly URLs by vBSEO 3.2.0
Copyright 2008 @ FPGA Central. All rights reserved