Synplify Pro, and I believe others, can synthesize descriptions of DDR
output registers (in the IOB's). However, I would not use just else,
but "elsif falling_edge(clk)" even in testbench code, since there are
events on signals that may not be either edge (transition from H to 1,
etc.) The template may require the second edge condition, not just an
else, especially if there is an async reset.
Finally, at least synplify pro, precision and I think Quartus allow
both edges in one process regardless of whether it can be targetted to
a DDR IOB register, but you cannot assign to the same variable/signal
on both edges.
If you truly need dual edge functionality in the body of the
FPGA
(with only SDR flops), something like the following will work without
glitches and with no clock gating:
qr <= d xor qf when rising_edge(clk);
qf <= d xor qr when falling_edge(clk);
q <= qr xor qf;
Synplify pro and quartus allow the above to be rewritten in a single
process with variables. The last time I tried it (several months ago,
they may have it fixed by now), Precision did not implement the
following correctly. XST does not allow this style.
process (clk) is
variable qr, qf : std_logic;
begin
if rising_edge(clk) then
qr := d xor qf; -- registered encode
elsif falling_edge(clk) then
qf := d xor qr; -- registered encode
end if;
q <= qr xor qf; -- combinatorial decode
end process;
Andy