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  #1 (permalink)  
Old 03-17-2007, 08:28 AM
Ulsk
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Default Xilinx XST 9.1, Verilog 2-D arrays, always @*

I noticed XST 9.1 still doesn't support multi-dim arrays in an always @*
block.
Here's a (perhaps poor) example:

reg signed [15:0] table [0:255];
reg signed [23:0] sum;

integer i;
always @*
begin
sum = 0;
for ( i =0; i < 256; i = i + 1 )
sum = sum + table[i]; // yes, I know this will synthesize a suboptimal
imbalanced adder-tree!
end


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  #2 (permalink)  
Old 03-17-2007, 10:53 AM
Homuncilus
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Default Re: Xilinx XST 9.1, Verilog 2-D arrays, always @*

On 3月17日, 下午2时28分, "Ulsk" <[email protected]> wrote:
> I noticed XST 9.1 still doesn't support multi-dim arrays in an always @*
> block.
> Here's a (perhaps poor) example:
>
> reg signed [15:0] table [0:255];
> reg signed [23:0] sum;
>
> integer i;
> always @*
> begin
> sum = 0;
> for ( i =0; i < 256; i = i + 1 )
> sum = sum + table[i]; // yes, I know this will synthesize a suboptimal
> imbalanced adder-tree!
> end


I think the code can not be synthesize correctly by any tool not only
ISE!

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  #3 (permalink)  
Old 03-18-2007, 12:17 AM
Ulsk
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Posts: n/a
Default Re: Xilinx XST 9.1, Verilog 2-D arrays, always @*

> "Homuncilus" <[email protected]> wrote in message
> news:[email protected] oups.com...
> On 3??17è?, ????2ê±28·?, "Ulsk" <[email protected]> wrote:
> I noticed XST 9.1 still doesn't support multi-dim arrays in an always @*
> > block.
> > Here's a (perhaps poor) example:
> >
> > reg signed [15:0] table [0:255];
> > reg signed [23:0] sum;
> >
> > integer i;
> > always @*
> > begin
> > sum = 0;
> > for ( i =0; i < 256; i = i + 1 )
> > sum = sum + table[i]; // yes, I know this will synthesize a
> > suboptimal
> > imbalanced adder-tree!
> > end

>
> I think the code can not be synthesize correctly by any tool not only
> ISE!


ASIC synthesis tools (like Synopsys Design Compiler, Cadence RTL
Compiler, etc.) have no difficulty synthesizing the above example.


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  #4 (permalink)  
Old 03-18-2007, 08:00 AM
Homuncilus
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Posts: n/a
Default Re: Xilinx XST 9.1, Verilog 2-D arrays, always @*

On 3鏈18鏃, 涓婂崍6鏃17鍒, "Ulsk" <[email protected]> wrote:
> > "Homuncilus" <[email protected]> wrote in message
> >news:[email protected] roups.com...
> > On 3??17篓篓?, ????2篓潞隆脌28隆陇?, "Ulsk" <[email protected]> wrote:
> > I noticed XST 9.1 still doesn't support multi-dim arrays in an always @*
> > > block.
> > > Here's a (perhaps poor) example:

>
> > > reg *signed [15:0] table [0:255];
> > > reg *signed [23:0] sum;

>
> > > integer i;
> > > always @*
> > > begin
> > > * sum = 0;
> > > * for ( i =0; i < 256; i = i + 1 )
> > > * * sum = sum + table[i]; *// yes, I know this will synthesize a
> > > suboptimal
> > > imbalanced adder-tree!
> > > end

>
> > I think the code can not be synthesize correctly by any tool not only
> > ISE!

>
> ASIC synthesis tools (like Synopsys Design Compiler, Cadence RTL
> Compiler, etc.) have no difficulty synthesizing the above example.- 闅愯棌琚紩鐢ㄦ枃* -
>
> - 鏄剧ず寮曠敤鐨勬枃* -


Could you tell me the result about the above example being synthesized
by the ASIC tools and could you sure that the function runs well?

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  #5 (permalink)  
Old 03-19-2007, 05:00 AM
John McGrath
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Posts: n/a
Default Re: Xilinx XST 9.1, Verilog 2-D arrays, always @*

On Mar 16, 11:28 pm, "Ulsk" <[email protected]> wrote:
> I noticed XST 9.1 still doesn't support multi-dim arrays in an always @*
> block.
> Here's a (perhaps poor) example:
>
> reg signed [15:0] table [0:255];
> reg signed [23:0] sum;
>
> integer i;
> always @*
> begin
> sum = 0;
> for ( i =0; i < 256; i = i + 1 )
> sum = sum + table[i]; // yes, I know this will synthesize a suboptimal
> imbalanced adder-tree!
> end


Correct me if I'm wrong, but I believe that this is not valid verilog
- you cannot use an array as a term in the always() sensitivity list,
and the always* implies that the array is in the sensitivity list. I
know that the ncverilog simulator warns about this (but does work). It
states that this is non-portable verilog. Synopsys DC does indeed
synthesize this correctly, but it's not a good idea to use non-
standard verilog statements. ISE seems to err on the side of adhering
to the strict rules of the verilog language. I could be wrong about
this, but from the warning given by ncverilog, I believe this to be
the case. Maybe try a verilog linting tool? formality/conformal should
set you straight, if you have them.
Cheers
John

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  #6 (permalink)  
Old 03-19-2007, 02:59 PM
Homuncilus
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Posts: n/a
Default Re: Xilinx XST 9.1, Verilog 2-D arrays, always @*

On Mar 19, 11:00 am, "John McGrath" <[email protected]> wrote:
> On Mar 16, 11:28 pm, "Ulsk" <[email protected]> wrote:
>
> > I noticed XST 9.1 still doesn't support multi-dim arrays in an always @*
> > block.
> > Here's a (perhaps poor) example:

>
> > reg signed [15:0] table [0:255];
> > reg signed [23:0] sum;

>
> > integer i;
> > always @*
> > begin
> > sum = 0;
> > for ( i =0; i < 256; i = i + 1 )
> > sum = sum + table[i]; // yes, I know this will synthesize a suboptimal
> > imbalanced adder-tree!
> > end

>
> Correct me if I'm wrong, but I believe that this is not valid verilog
> - you cannot use an array as a term in the always() sensitivity list,
> and the always* implies that the array is in the sensitivity list. I
> know that the ncverilog simulator warns about this (but does work). It
> states that this is non-portable verilog. Synopsys DC does indeed
> synthesize this correctly, but it's not a good idea to use non-
> standard verilog statements. ISE seems to err on the side of adhering
> to the strict rules of the verilog language. I could be wrong about
> this, but from the warning given by ncverilog, I believe this to be
> the case. Maybe try a verilog linting tool? formality/conformal should
> set you straight, if you have them.
> Cheers
> John


I think the wrong isn't due to the sensitivity list. Do you sure the
error in ISE is caused by that?

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  #7 (permalink)  
Old 03-19-2007, 04:31 PM
John McGrath
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Posts: n/a
Default Re: Xilinx XST 9.1, Verilog 2-D arrays, always @*

On Mar 19, 5:59 am, "Homuncilus" <[email protected]> wrote:
> On Mar 19, 11:00 am, "John McGrath" <[email protected]> wrote:
>
>
>
> > On Mar 16, 11:28 pm, "Ulsk" <[email protected]> wrote:

>
> > > I noticed XST 9.1 still doesn't support multi-dim arrays in an always @*
> > > block.
> > > Here's a (perhaps poor) example:

>
> > > reg signed [15:0] table [0:255];
> > > reg signed [23:0] sum;

>
> > > integer i;
> > > always @*
> > > begin
> > > sum = 0;
> > > for ( i =0; i < 256; i = i + 1 )
> > > sum = sum + table[i]; // yes, I know this will synthesize a suboptimal
> > > imbalanced adder-tree!
> > > end

>
> > Correct me if I'm wrong, but I believe that this is not valid verilog
> > - you cannot use an array as a term in the always() sensitivity list,
> > and the always* implies that the array is in the sensitivity list. I
> > know that the ncverilog simulator warns about this (but does work). It
> > states that this is non-portable verilog. Synopsys DC does indeed
> > synthesize this correctly, but it's not a good idea to use non-
> > standard verilog statements. ISE seems to err on the side of adhering
> > to the strict rules of the verilog language. I could be wrong about
> > this, but from the warning given by ncverilog, I believe this to be
> > the case. Maybe try a verilog linting tool? formality/conformal should
> > set you straight, if you have them.
> > Cheers
> > John

>
> I think the wrong isn't due to the sensitivity list. Do you sure the
> error in ISE is caused by that?


I ran the following testcase through ncverilog:

module test;

reg [7:0] array [0:7];
reg [2:0] idx;
reg [7:0] out;

[email protected]*
begin
out = array[idx];
end

endmodule


The logfile gives the following warnings:

[email protected]*
|
ncvlog: *W,STARMR (array.v,8|6): @* containing memory reference not
standard or portable.
out = array[idx];
ncvlog: *W,MRSTAR (array.v,10|11): memory reference that was not
standard in @*.
module worklib.test:v

So clearly always @* when used with an array is non part of the
verilog standard.

Cheers
John

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  #8 (permalink)  
Old 03-19-2007, 04:35 PM
bluesclues
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Posts: n/a
Default Re: Xilinx XST 9.1, Verilog 2-D arrays, always @*

On Mar 19, 7:31 am, "John McGrath" <[email protected]> wrote:
> On Mar 19, 5:59 am, "Homuncilus" <[email protected]> wrote:
>
>
>
> > On Mar 19, 11:00 am, "John McGrath" <[email protected]> wrote:

>
> > > On Mar 16, 11:28 pm, "Ulsk" <[email protected]> wrote:

>
> > > > I noticed XST 9.1 still doesn't support multi-dim arrays in an always @*
> > > > block.
> > > > Here's a (perhaps poor) example:

>
> > > > reg signed [15:0] table [0:255];
> > > > reg signed [23:0] sum;

>
> > > > integer i;
> > > > always @*
> > > > begin
> > > > sum = 0;
> > > > for ( i =0; i < 256; i = i + 1 )
> > > > sum = sum + table[i]; // yes, I know this will synthesize a suboptimal
> > > > imbalanced adder-tree!
> > > > end

>
> > > Correct me if I'm wrong, but I believe that this is not valid verilog
> > > - you cannot use an array as a term in the always() sensitivity list,
> > > and the always* implies that the array is in the sensitivity list. I
> > > know that the ncverilog simulator warns about this (but does work). It
> > > states that this is non-portable verilog. Synopsys DC does indeed
> > > synthesize this correctly, but it's not a good idea to use non-
> > > standard verilog statements. ISE seems to err on the side of adhering
> > > to the strict rules of the verilog language. I could be wrong about
> > > this, but from the warning given by ncverilog, I believe this to be
> > > the case. Maybe try a verilog linting tool? formality/conformal should
> > > set you straight, if you have them.
> > > Cheers
> > > John

>
> > I think the wrong isn't due to the sensitivity list. Do you sure the
> > error in ISE is caused by that?

>
> I ran the following testcase through ncverilog:
>
> module test;
>
> reg [7:0] array [0:7];
> reg [2:0] idx;
> reg [7:0] out;
>
> [email protected]*
> begin
> out = array[idx];
> end
>
> endmodule
>
> The logfile gives the following warnings:
>
> [email protected]*
> |
> ncvlog: *W,STARMR (array.v,8|6): @* containing memory reference not
> standard or portable.
> out = array[idx];
> ncvlog: *W,MRSTAR (array.v,10|11): memory reference that was not
> standard in @*.
> module worklib.test:v
>
> So clearly always @* when used with an array is non part of the
> verilog standard.
>
> Cheers
> John



You could alternately use:

always @(idx) in place of [email protected]*

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  #9 (permalink)  
Old 03-19-2007, 05:08 PM
John McGrath
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Posts: n/a
Default Re: Xilinx XST 9.1, Verilog 2-D arrays, always @*

On Mar 19, 7:35 am, "bluesclues" <[email protected]> wrote:
> On Mar 19, 7:31 am, "John McGrath" <[email protected]> wrote:
>
>
>
> > On Mar 19, 5:59 am, "Homuncilus" <[email protected]> wrote:

>
> > > On Mar 19, 11:00 am, "John McGrath" <[email protected]> wrote:

>
> > > > On Mar 16, 11:28 pm, "Ulsk" <[email protected]> wrote:

>
> > > > > I noticed XST 9.1 still doesn't support multi-dim arrays in an always @*
> > > > > block.
> > > > > Here's a (perhaps poor) example:

>
> > > > > reg signed [15:0] table [0:255];
> > > > > reg signed [23:0] sum;

>
> > > > > integer i;
> > > > > always @*
> > > > > begin
> > > > > sum = 0;
> > > > > for ( i =0; i < 256; i = i + 1 )
> > > > > sum = sum + table[i]; // yes, I know this will synthesize a suboptimal
> > > > > imbalanced adder-tree!
> > > > > end

>
> > > > Correct me if I'm wrong, but I believe that this is not valid verilog
> > > > - you cannot use an array as a term in the always() sensitivity list,
> > > > and the always* implies that the array is in the sensitivity list. I
> > > > know that the ncverilog simulator warns about this (but does work). It
> > > > states that this is non-portable verilog. Synopsys DC does indeed
> > > > synthesize this correctly, but it's not a good idea to use non-
> > > > standard verilog statements. ISE seems to err on the side of adhering
> > > > to the strict rules of the verilog language. I could be wrong about
> > > > this, but from the warning given by ncverilog, I believe this to be
> > > > the case. Maybe try a verilog linting tool? formality/conformal should
> > > > set you straight, if you have them.
> > > > Cheers
> > > > John

>
> > > I think the wrong isn't due to the sensitivity list. Do you sure the
> > > error in ISE is caused by that?

>
> > I ran the following testcase through ncverilog:

>
> > module test;

>
> > reg [7:0] array [0:7];
> > reg [2:0] idx;
> > reg [7:0] out;

>
> > [email protected]*
> > begin
> > out = array[idx];
> > end

>
> > endmodule

>
> > The logfile gives the following warnings:

>
> > [email protected]*
> > |
> > ncvlog: *W,STARMR (array.v,8|6): @* containing memory reference not
> > standard or portable.
> > out = array[idx];
> > ncvlog: *W,MRSTAR (array.v,10|11): memory reference that was not
> > standard in @*.
> > module worklib.test:v

>
> > So clearly always @* when used with an array is non part of the
> > verilog standard.

>
> > Cheers
> > John

>
> You could alternately use:
>
> always @(idx) in place of [email protected]*


Maybe, but it would not work if the contents of the array were updated
by a different process, independent of idx.
I'm not sure how this would be syntesized - It may infer latches on
the output, or error out. I'd be interested to see what happens

Personally, for this example (asynch read of array elements) I'd use a
continuous assignment.

But personally I think verilog language should support @* in an array
context, it works in all other contexts, and prevents unintentional
latch inferral.
As we can see from Duth, this will be added to ISE soon, and some
other tools support it too, but they just warn that it is not strictly
part of the standard.

Cheers
John

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  #10 (permalink)  
Old 03-19-2007, 06:17 PM
Guest
 
Posts: n/a
Default Re: Xilinx XST 9.1, Verilog 2-D arrays, always @*

On Mar 16, 11:28 pm, "Ulsk" <[email protected]> wrote:
> I noticed XST 9.1 still doesn't support multi-dim arrays in an always @*
> block.
> Here's a (perhaps poor) example:
>
> reg signed [15:0] table [0:255];
> reg signed [23:0] sum;
>
> integer i;
> always @*
> begin
> sum = 0;
> for ( i =0; i < 256; i = i + 1 )
> sum = sum + table[i]; // yes, I know this will synthesize a suboptimal
> imbalanced adder-tree!
> end


Ulsk,

I've heard that this is a "grey" area of the Verilog standard. It
shouldn't be at
all - the intended behavior is quite clear in your example, and the
tools should do the correct thing. Unfortunetly XST doesn't get it
right yet.
Xilinx promised to fix this is ISE9.x. Now, they've put it off again
until 10.x.

We've used VERY similar constructs - except we used SystemVerilog
packed arrays, instead of your
verilog-2001 "unpacked" array equivalent. This has worked fine for us
in ASIC and FPGA flows.
It works with VCS, modelsim, dc_shell, and Precision. Of course,
you'll need to use the
"Systemverilog" switch of the tools - which Xilinx doesn't have yet
either.

For your example in SystemVerilog, just change the table definition
to:
reg signed [ 255 : 0 ] [ 15 : 0 ] table;

And it would work. I'm thinking in the IEEE Std 1800-2005
(SystemVerilog IEEE standard),
they may have cleaned this up, and you're original example would work.

--Mark







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