FPGA Central

Hi,

When PLI is uded in VCS or other simulator, we can define 3 functions
for one custom system call in Verilog ("check" "call" "misc"). Why do
we need "check" "call" "misc" in PLI? Since only one system call, we
only need to associate one function with it, right?


Thanks,

Lee wrote:
> Hi,
>
> When PLI is uded in VCS or other simulator, we can define 3 functions
> for one custom system call in Verilog ("check" "call" "misc"). Why do
> we need "check" "call" "misc" in PLI? Since only one system call, we
> only need to associate one function with it, right?
>
>
> Thanks,

Cut and pasted from the standard...

A checktf PLI application shall be called when the user-defined system
task or function name is encountered
during parsing or compiling the Verilog HDL source code.

A calltf PLI application shall be called each time the associated
user-defined system task or function is executed
within the Verilog HDL source code.

A misctf PLI application shall be called by a Verilog software product
for miscellaneous reasons while the
Verilog HDL source description is being executed. Among these reasons
can be the end of a simulation time
step, a logic value change on a user-defined system task/function
argument, or the execution of the $stop
and $finish built-in system tasks.

/Ed