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Old 05-19-2005, 06:50 AM
abilash
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Default Why do VHDL gate level models simulate slower than verilog

Hi Group,
I am not sure if this is the right group to post this
query,but I am doing it anyway.I am relatively new to VHDL and am tring
to understand why
VHDL gate level descriptions simulate slower than verilog models.I was
told that it was because how the VHDL model gets evaluated (delay
models) that makes it slower.I didnt quite follow this and if somebody
in the group could point me towards a more detailed explanation ,it
would be great.I would also like to know why do we see better VHDL
performace at behavioural descriptions(as compared to verilog
behavioural descriptions.).I am sorry if this has been discussed
previously.

Thanks,
Abilash.

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