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  #1 (permalink)  
Old 07-02-2005, 03:32 AM
Davy
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Default What's wrong with this verilog?

Hi all,
I want to use OVL (http://www.eda.org/ovl/) to start learning assert.
Verilog version was used.
The .h and .vlib file has been changed to .v.
But the file seems have compile error.

(Modelsim 5.6)ERROR: D:/Modeltech_5.6/test/ovl_task.v(1): near "task":
expecting:
MACROMODULE MODULE PRIMITIVE (*

//------- part of ovl_task.h-----------
task ovl_error;
input [8*63:0] err_msg;
begin
error_count = error_count + 1;
`ifdef ASSERT_MAX_REPORT_ERROR
if (error_count <= `ASSERT_MAX_REPORT_ERROR)
`endif
$display("OVL_ERROR : %s : %s : %0s : severity %0d : time %0t :
%m",
assert_name, msg, err_msg, severity_level, $time);
if (severity_level == 0) ovl_finish;
end
endtask
//-------------------------------------

Three files have been packeted
(assert_always.vlib,ovl_header.h,ovl_task.h).

Any suggestions will be appreciated!
Best regards,
Davy

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  #2 (permalink)  
Old 07-03-2005, 05:29 PM
Peng Cong
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Default Re: What's wrong with this verilog?

task should be included in a module

"Davy" <[email protected]> ????
news:[email protected] oups.com...
> Hi all,
> I want to use OVL (http://www.eda.org/ovl/) to start learning assert.
> Verilog version was used.
> The .h and .vlib file has been changed to .v.
> But the file seems have compile error.
>
> (Modelsim 5.6)ERROR: D:/Modeltech_5.6/test/ovl_task.v(1): near "task":
> expecting:
> MACROMODULE MODULE PRIMITIVE (*
>
> //------- part of ovl_task.h-----------
> task ovl_error;
> input [8*63:0] err_msg;
> begin
> error_count = error_count + 1;
> `ifdef ASSERT_MAX_REPORT_ERROR
> if (error_count <= `ASSERT_MAX_REPORT_ERROR)
> `endif
> $display("OVL_ERROR : %s : %s : %0s : severity %0d : time %0t :
> %m",
> assert_name, msg, err_msg, severity_level, $time);
> if (severity_level == 0) ovl_finish;
> end
> endtask
> //-------------------------------------
>
> Three files have been packeted
> (assert_always.vlib,ovl_header.h,ovl_task.h).
>
> Any suggestions will be appreciated!
> Best regards,
> Davy
>



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  #3 (permalink)  
Old 07-03-2005, 09:27 PM
Chris F Clark
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Default Re: What's wrong with this verilog?

To hoepfully make the point a little more clear, the two .h files
ovl_header.h and ovl_task.h were not meant to be converted into
stand-alone .v files. they were meant to be `included into other .v
files. In particular, ovl_task.h was meant to be included in the
assert_xxx.v (where xxx is the assertion name) files (i.e. the files
that were originally given the .vlib suffix) and ovl_header.h was
meant to be included into a user written .v file that uses assertions.

-Chris
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  #4 (permalink)  
Old 07-04-2005, 09:14 AM
Davy
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Default Re: What's wrong with this verilog?

Hi Chris,

I copy ovl_task to assert_xxx.v, set some Macro. And all O.K.!

Thanks!
Davy

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