On Aug 30, 8:54 am, "
[email protected]" <
[email protected]>
wrote:
> Are you talking of something like this
>
> module top ( input a );
> endmodule
That would be one example. It doesn't need to be in a module port
list.
In Verilog you can also have wires that are neither driven nor used.
More examples:
module top ( input a );
wire b
wire c
assign c = 1'b1;
endmodule
Here a is an unused input, presumably driven exernally. This
and c, which has an assignment but doesn't appear on the RHS
of any expression, are examples of wires with one end dangling.
Wire b is completely unconnected or dangling at both ends if
you like to think of it that way. Normally this example
would give warnings for each case, but no errors. Synthesis
tools may give you an error due to the complete lack of
synthesized logic in this example, but in the presence of
other normal logic, this would again just create warnings.