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  #1 (permalink)  
Old 01-30-2004, 11:40 PM
MarcoŠ
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Default wait statement with Xilinx ise webpack4.2

Hi! I'm an engineer student and having some problems with xilinx ise webpack
4.2

I have to realize an interface module which waits for a signal from a
transmitter module before transferring the data from a bidirectional bus to
the tx module...the problem is that i couldn't synthesize it because the
compiler reports the following error:

ERROR:Xst:850 - "UART_control.v", line 42: Unsupported Wait Statement.

Here is the code:

always @(negedge NRD)
begin

wait (oktx);

i_readout <= 0;

wait (oktx);

i_res <= 1;
i_readout <= 1;

end


How could i realize the same function without the wait statement? I tried
with a while construct without success...

Thanks in advance to all


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  #2 (permalink)  
Old 02-01-2004, 02:01 AM
Jim Wu
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Default Re: wait statement with Xilinx ise webpack4.2

> How could i realize the same function without the wait statement? I tried
> with a while construct without success...
>



"wait" statement is not synthesizable. Try to use a state machine.

[email protected] (remove capital letters)
http://www.geocities.com/jimwu88/chips


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  #3 (permalink)  
Old 02-02-2004, 05:45 PM
Andy Peters
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Default Re: wait statement with Xilinx ise webpack4.2

"MarcoŠ" <[email protected]> wrote in message news:<[email protected]>. ..
> Hi! I'm an engineer student and having some problems with xilinx ise webpack
> 4.2
>
> I have to realize an interface module which waits for a signal from a
> transmitter module before transferring the data from a bidirectional bus to
> the tx module...the problem is that i couldn't synthesize it because the
> compiler reports the following error:
>
> ERROR:Xst:850 - "UART_control.v", line 42: Unsupported Wait Statement.
>
> Here is the code:
>
> always @(negedge NRD)
> begin
>
> wait (oktx);
>
> i_readout <= 0;
>
> wait (oktx);
>
> i_res <= 1;
> i_readout <= 1;
>
> end
>
>
> How could i realize the same function without the wait statement? I tried
> with a while construct without success...


RTFM. The synthesis manual has a section about "non-synthesizable
constructs."

Looks like you're trying to design something that looks for the
assertion of a read enable, and when the thing doing to the reading
grabs the data gets it, then you continue. Or something.

Unfortunately, you'll need to recode your logic. As the other poster
said, a state machine is a good thing. You might consider asking your
instructor to help you understand why your code is not correct. You
might further consider asking him to explain the "synthesizable
Verilog subset."

--a
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  #4 (permalink)  
Old 02-03-2004, 08:34 AM
Sajan
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Posts: n/a
Default Re: wait statement with Xilinx ise webpack4.2

Try implementing the same using an "if" statement.
Things should work fine then.


"MarcoŠ" <[email protected]> wrote in message news:<[email protected]>. ..
> Hi! I'm an engineer student and having some problems with xilinx ise webpack
> 4.2
>
> I have to realize an interface module which waits for a signal from a
> transmitter module before transferring the data from a bidirectional bus to
> the tx module...the problem is that i couldn't synthesize it because the
> compiler reports the following error:
>
> ERROR:Xst:850 - "UART_control.v", line 42: Unsupported Wait Statement.
>
> Here is the code:
>
> always @(negedge NRD)
> begin
>
> wait (oktx);
>
> i_readout <= 0;
>
> wait (oktx);
>
> i_res <= 1;
> i_readout <= 1;
>
> end
>
>
> How could i realize the same function without the wait statement? I tried
> with a while construct without success...
>
> Thanks in advance to all

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