FPGA Central - World's 1st FPGA / CPLD Portal

FPGA Central

World's 1st FPGA Portal


Go Back   FPGA Groups > NewsGroup > Verilog

Verilog comp.lang.verilog newsgroup / usenet

LinkBack Thread Tools Display Modes
  #1 (permalink)  
Old 07-24-2003, 10:30 AM
Jan Decaluwe
Posts: n/a
Default Verilog VCD and string literals

With gtkwave, I can view VCD files that contain
string literals. For example, if variable "string"
is defined as follows in the VCD file:

$var real 1 @ string $end

then string literals can be dumped as follows:

sThe @

Note the 's' qualifier.

My question is: is this part of the VCD standard,
or is it a gtkwave specific extension?
In other words, can such VCD files be viewed
with other waveform viewers?

I have not been able to find anything about
this functionality in VCD-related documents
on the web.

Regards, Jan

Jan Decaluwe - Resources bvba
Losbergenlaan 16, B-3010 Leuven, Belgium
mailto:[email protected]
Reply With Quote


Thread Tools
Display Modes

Posting Rules
You may not post new threads
You may not post replies
You may not post attachments
You may not edit your posts

BB code is On
Smilies are On
[IMG] code is On
HTML code is Off
Trackbacks are On
Pingbacks are On
Refbacks are On

All times are GMT +1. The time now is 01:45 PM.

Powered by vBulletin® Version 3.8.0
Copyright ©2000 - 2020, Jelsoft Enterprises Ltd.
Search Engine Friendly URLs by vBSEO 3.2.0
Copyright 2008 @ FPGA Central. All rights reserved