FPGA Central - World's 1st FPGA / CPLD Portal

FPGA Central

World's 1st FPGA Portal

 

Go Back   FPGA Groups > NewsGroup > Verilog

Verilog comp.lang.verilog newsgroup / usenet

Reply
 
LinkBack Thread Tools Display Modes
  #1 (permalink)  
Old 07-17-2003, 06:18 PM
Peng Yu
Guest
 
Posts: n/a
Default verilog syntax question

Hi,
In the following code list, I understand something like
..SECS(CONNECT5)? What does the point mean? And what do the variables
within the parentheses mean?
Thanks!
Peng

module TIME_BLOCK ( SET_TIME, HRS, MINS, CLK, CONNECT6,
CONNECT7,
CONNECT8 );
input SET_TIME, HRS, MINS, CLK;
output [3:0] CONNECT6;
output [5:0] CONNECT7;
output CONNECT8;
wire CONNECT3, CONNECT4, CONNECT5;
TIME_STATE_MACHINE U1 ( .TIME_BUTTON(SET_TIME),
..HOURS_BUTTON(HRS),
.MINUTES_BUTTON(MINS), .CLK(CLK), .SECS(CONNECT5),
..HOURS(CONNECT3),
.MINS(CONNECT4) );
TIME_COUNTER U2 ( .SECS(CONNECT5), .HOURS(CONNECT3),
..MINS(CONNECT4),
.CLK(CLK), .HOURS_OUT(CONNECT6),
.MINUTES_OUT(CONNECT7) ,
.AM_PM_OUT(CONNECT8) );
endmodule
Reply With Quote
  #2 (permalink)  
Old 07-17-2003, 09:58 PM
Andrew Paule
Guest
 
Posts: n/a
Default Re: verilog syntax question

Hi Peng:

it's how you use a port from another module.

Let's say that we have a module like a buffer -

module BUF (A, Y)

to instantiate this in a file

PengsBuf Buf (.A(PengsInput),
.B(PengsOutput));

this would assign PengsInput to the A port of the buffer, and
PengsOutput to the Y port of the buffer

Andrew

Peng Yu wrote:

>Hi,
> In the following code list, I understand something like
>.SECS(CONNECT5)? What does the point mean? And what do the variables
>within the parentheses mean?
>Thanks!
>Peng
>
>module TIME_BLOCK ( SET_TIME, HRS, MINS, CLK, CONNECT6,
> CONNECT7,
> CONNECT8 );
>input SET_TIME, HRS, MINS, CLK;
>output [3:0] CONNECT6;
>output [5:0] CONNECT7;
>output CONNECT8;
> wire CONNECT3, CONNECT4, CONNECT5;
> TIME_STATE_MACHINE U1 ( .TIME_BUTTON(SET_TIME),
>.HOURS_BUTTON(HRS),
> .MINUTES_BUTTON(MINS), .CLK(CLK), .SECS(CONNECT5),
>.HOURS(CONNECT3),
> .MINS(CONNECT4) );
> TIME_COUNTER U2 ( .SECS(CONNECT5), .HOURS(CONNECT3),
>.MINS(CONNECT4),
> .CLK(CLK), .HOURS_OUT(CONNECT6),
> .MINUTES_OUT(CONNECT7) ,
> .AM_PM_OUT(CONNECT8) );
>endmodule
>
>


Reply With Quote
  #3 (permalink)  
Old 07-18-2003, 12:09 AM
Andy Peters
Guest
 
Posts: n/a
Default Re: verilog syntax question

[email protected] (Peng Yu) wrote in message news:<[email protected] com>...
> Hi,
> In the following code list, I understand something like
> .SECS(CONNECT5)? What does the point mean? And what do the variables
> within the parentheses mean?


You might want to purchase a Verilog book!

> TIME_STATE_MACHINE U1 ( .TIME_BUTTON(SET_TIME),
> .HOURS_BUTTON(HRS),
> .MINUTES_BUTTON(MINS), .CLK(CLK), .SECS(CONNECT5),
> .HOURS(CONNECT3),
> .MINS(CONNECT4) );
> TIME_COUNTER U2 ( .SECS(CONNECT5), .HOURS(CONNECT3),
> .MINS(CONNECT4),
> .CLK(CLK), .HOURS_OUT(CONNECT6),
> .MINUTES_OUT(CONNECT7) ,
> .AM_PM_OUT(CONNECT8) );


You're instantiating a module called TIME_STATE_MACHINE. This module
has a number of ports.

Verilog allows you to connect the module's ports to external signals
in two ways: by order, or by name. Your module instantiation uses the
latter (which I prefer).

The connection:

.TIME_BUTTON(SET_TIME)

connects a net that's *inside* the module, called TIME_BUTTON, to a
net in the instantiating module, called SET_TIME.

HTH,
a
Reply With Quote
Reply

Bookmarks

Thread Tools
Display Modes

Posting Rules
You may not post new threads
You may not post replies
You may not post attachments
You may not edit your posts

BB code is On
Smilies are On
[IMG] code is On
HTML code is Off
Trackbacks are On
Pingbacks are On
Refbacks are On



All times are GMT +1. The time now is 01:37 PM.


Powered by vBulletin® Version 3.8.0
Copyright ©2000 - 2020, Jelsoft Enterprises Ltd.
Search Engine Friendly URLs by vBSEO 3.2.0
Copyright 2008 @ FPGA Central. All rights reserved