FPGA Central

hello all

can anyone help me?

I want to model large memories in verilog.But you know that for
modeling for example 1M RAM memory about 32M in system is requierd.

so it will be fine if we could model the RAM elements in PLI.

can anyone help me for writing or finding such PLI?


with very best wishes

If you use VCS, it has a sparse memory model.

You may also want to take a look at TestBuilder which has support for
sparse memory model as well.

HTH,
Jim ([email protected] remve NOOOSPAM)
http://www.geocities.com/jimwu88/chips


morteza wrote:
> hello all
>
> can anyone help me?
>
> I want to model large memories in verilog.But you know that for
> modeling for example 1M RAM memory about 32M in system is requierd.
>
> so it will be fine if we could model the RAM elements in PLI.
>
> can anyone help me for writing or finding such PLI?
>
>
> with very best wishes

morteza wrote:

> hello all
>
> can anyone help me?
>
> I want to model large memories in verilog.But you know that for
> modeling for example 1M RAM memory about 32M in system is requierd.
>
> so it will be fine if we could model the RAM elements in PLI.
>
> can anyone help me for writing or finding such PLI?

We have it in the Doulos Verilog Training Course (in the course and
as an exercise).
I checked in the free Doulos Know-How section on the Web : it's not there,
so I suggest you try and contact the Doulos UK office directly.

It's not difficult, so maybe a good book on PLI has it as an example ?
(Stuart Sutherland's ?)

Another possibility is to ask Ram vendors for behavioral Verilog models
(and keep the part you're interested in)

I don't dare to post this here : but the solution in VHDL is very easy
thanks to access type ;-)
Aren't we all eager to get SystemVerilog in our favorite tools ???

Last : Janick's Verification Guild has also a couple of useful pointers.

Bert Cuzeau