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  #1 (permalink)  
Old 05-04-2006, 05:18 AM
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Default verilog multidimentional arrays


using verilog how to write a module which has an inpput port for an
array of 8 bit signals and how to write a test bench for it.

thank you.

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  #2 (permalink)  
Old 05-04-2006, 07:15 PM
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Default Re: verilog multidimentional arrays

Verilog-2001 supports multi-dimensional arrays and arrays of nets, but
you still cannot connect an entire array to a port. You can only
connect scalars or vectors to ports. The arrays of nets were primarily
intended for connection to multiple module instances created by
generate loops.

SystemVerilog allows connection of entire arrays to ports (which is
related to the fact that it also allows you to assign entire arrays to
each other).

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Old 05-08-2006, 07:01 PM
Jeremy Ralph
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Default Re: verilog multidimentional arrays

There are some tricks one can use to map an array to a port. In
Verilog-2001 you can use arrays within the module then for the ports
flatten the array into a vector. Silly that Verilog doesn't support
multi-d arrays in ports. Glad to see this in SV. Of course arrays are
useful for all kinds of things beyond connecting module instances
created by generate loops... for example time sliced state-machines,
channelized logic, parameterized modules etc.

PDTi [ http://www.productive-eda.com ]
SpectaReg -- Spec-down code and doc generation for register maps

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