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  #1 (permalink)  
Old 03-02-2004, 06:35 PM
Marty
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Default Verilog Instance Arrays and Synopsys DC?

Hi,

I've got some code that is configurable based a macro named BUS_WIDTH. The
code basically instantiates BUS_WIDTH number of MUX circuits. The code is
something like this:

mux_delay mux_delay_inst[`BUS_WIDTH-1:0]
(
.s (1'b1),
.a (1'b1),
.b (fixed_delay),
.z (addr_out['BUS_WIDTH-1:0])
);

Synopsys DC (version U2003.06-2) generates an error for this code. Does
Synopsys DC support an instance array?

I wanted to use Verilog 2001 generate, but was told not to for this project.

Thanks for the help.
--
Marty


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  #2 (permalink)  
Old 03-04-2004, 04:49 AM
nospam
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Default Re: Verilog Instance Arrays and Synopsys DC?

> I've got some code that is configurable based a macro named BUS_WIDTH. The
> code basically instantiates BUS_WIDTH number of MUX circuits. The code is
> something like this:
>
> mux_delay mux_delay_inst[`BUS_WIDTH-1:0]
> (
> .s (1'b1),
> .a (1'b1),
> .b (fixed_delay),
> .z (addr_out['BUS_WIDTH-1:0])
> );
>
> Synopsys DC (version U2003.06-2) generates an error for this code. Does
> Synopsys DC support an instance array?


Yes, Synopsys DC has supported instance-arrays since 2001.08 or so.
(Instance-arrays are part of the Verilog-1995 LRM.) Cadence PKS,
Modelsim 5.6, Verilog-XL 4.0 and later all support them.

I assume 's', 'a', 'b', and 'z' are all single-bit (scalar) ports. And
that fixed_delay is actually "fixed_delay[`BUS_WIDTH-1:0]". The
correct instantiation looks like this...

mux_delay mux_delay_inst[`BUS_WIDTH-1:0]
(
.s ( {`BUS_WIDTH {1'b1}} ),
.a ( {`BUS_WIDTH {1'b1}} ),
.b ( fixed_delay ),
.z (addr_out['BUS_WIDTH-1:0])
);
// ^^^ Earlier versions of Design-Compiler didn't like the
// bit-replication "{{}}" operator when it's used as
// an argument for the instantiation.
//
// Below is a *safer* (and easier to read) version...

wire ['BUS_WIDTH-1:0] bus_a, bus_s, bus_b, bus_z;

assign bus_a = { `BUS_WIDTH { 1'b1 } }; // expand 1'b1 -> `BUS_WIDTH
assign bus_b = fixed_delay; // bits wide
assign bus_s = { `BUS_WIDTH { 1'b1 } };

mux_delay mux_delay_inst[`BUS_WIDTH-1:0]
(
.s ( bus_s ),
.a ( bus_a ),
.b ( fixed_delay ),
.z (addr_out['BUS_WIDTH-1:0])
);

..............................................

And of course, you can do array-instances for modules which
have vector-ports.

module my_adder( a, b, carry_in, sum );
parameter B_W = 8; // data-bus width (a, b, sum)
input [ (B_W-1):0 ] a;
input [ (B_W-1):0 ] b;
input carry_in;

output [ (B_W-1):0 ] sum;

assign sum = a + b + carry_in;

endmodule // my_adder( a, b, carry_in, sum)

module big_thing_of_riches;
// given to Hercules by the Lion...As told by Homer.

parameter D_W = 8; // data-width (of each adder element)
parameter NUM = 4; // number of adders

// build a parallel array of adders, independent of each other

wire [ (D_W*NUM)-1:0 ] bus_a, bus_b, bus_sum;
wire [ (NUM-1):0 ] bus_carry_in;

my_adder #( .B_W(D_W) ) // override my_adder's B_W parameter
(
// inputs
.a(bus_a), .b(bus_b), .carry_in(bus_carry_in),

// outpus
.sum(bus_sum)
);

// adder #1
assign bus_carry_in[0] = 1;
assign bus_a[ (D_W*1)-1 : (D_W*0) ] = 13;
assign bus_b[ (D_W*1)-1 : (D_W*0) ] = 17;
// bus_sum[ (D_W*1)-1 : (D_W*0) ] = 31

// adder #2
assign bus_carry_in[1] = 1;
assign bus_a[ (D_W*2)-1 : (D_W*1) ] = 4;
assign bus_b[ (D_W*2)-1 : (D_W*1) ] = 5;
// bus_sum[ (D_W*2)-1 : (D_W*1) ] = 10

// adder #NUM
assign bus_carry_in[1] = 0;
assign bus_a[ (D_W*NUM)-1 : D_W*(NUM-1) ] = 3;
assign bus_b[ (D_W*NUM)-1 : D_W*(NUM-1) ] = 1;
// bus_sum[ (D_W*NUM)-1 : D_W*(NUM-1) ] = 4

endmodule // big_thing_of_riches

>
> I wanted to use Verilog 2001 generate, but was told not to for this project.


A lot of tools don't completely support generate/endgenerate blocks,
especially if you use a lot of conditional (if/else) evaluations inside
the generate block.

As you can see from my above example, you have to 'prepare' the
wire-vector using annoying indexing-math. You can't directly pass
2D-wires/regs to an instance-array (at least Design_Compiler doesn't let
you.) A generate/endgenerate is much more convenient, because you can
explicitly assign *each* port on an *individual* basis...instead of
having to cleverly construct an aggregate vector (like I did above.)

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  #3 (permalink)  
Old 03-04-2004, 05:41 PM
Marty
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Posts: n/a
Default Re: Verilog Instance Arrays and Synopsys DC?

First, thanks for all the great feedback.

See inline comments below:

"nospam" <[email protected]> wrote in message
news:[email protected] om...
> > I've got some code that is configurable based a macro named BUS_WIDTH.

The
> > code basically instantiates BUS_WIDTH number of MUX circuits. The code

is
> > something like this:
> >
> > mux_delay mux_delay_inst[`BUS_WIDTH-1:0]
> > (
> > .s (1'b1),
> > .a (1'b1),
> > .b (fixed_delay),
> > .z (addr_out['BUS_WIDTH-1:0])
> > );
> >
> > Synopsys DC (version U2003.06-2) generates an error for this code. Does
> > Synopsys DC support an instance array?

>
> Yes, Synopsys DC has supported instance-arrays since 2001.08 or so.
> (Instance-arrays are part of the Verilog-1995 LRM.) Cadence PKS,
> Modelsim 5.6, Verilog-XL 4.0 and later all support them.
>
> I assume 's', 'a', 'b', and 'z' are all single-bit (scalar) ports. And
> that fixed_delay is actually "fixed_delay[`BUS_WIDTH-1:0]". The
> correct instantiation looks like this...


Yes; s, a, b, and z are scalar ports and so is fixed_delay. What I'm trying
to do is buffer the signal fixed_delay with `BUS_WIDTH number of mux_delay
components. Is my original syntax correct? I had no problem simulating
with Modelsim. But DC appears to choke on the first "[" in the instance
array.
--
Marty


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  #4 (permalink)  
Old 03-04-2004, 07:25 PM
Steven Sharp
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Posts: n/a
Default Re: Verilog Instance Arrays and Synopsys DC?

nospam <[email protected]> wrote in message news:<[email protected] com>...
>
> I assume 's', 'a', 'b', and 'z' are all single-bit (scalar) ports. And
> that fixed_delay is actually "fixed_delay[`BUS_WIDTH-1:0]". The
> correct instantiation looks like this...
>
> mux_delay mux_delay_inst[`BUS_WIDTH-1:0]
> (
> .s ( {`BUS_WIDTH {1'b1}} ),
> .a ( {`BUS_WIDTH {1'b1}} ),
> .b ( fixed_delay ),
> .z (addr_out['BUS_WIDTH-1:0])
> );


With a correct implementation of instance arrays, this replication
operation is not needed. If a port expression has the same bit
length as the port of a single instance, then it automatically
gets connected to the port of each of the instances. Otherwise
it must match the sum of the lengths of the port for all of the
instances, in which case part-selects of the value get connected
to each instance.
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