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  #1 (permalink)  
Old 06-07-2007, 12:15 PM
babu
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Posts: n/a
Default verilog HDL problem

what is the error in the following code. in it the main module is
"test". in that module's "always" block another module "counter" is
called. but it shows error. how can i solve the problem? how can i
call another module in always block?


module counter(clock, reset, count);
input clock, reset;
output [3:0] count;

reg [3:0] next_count,count;

[email protected]*
begin
if(count<15)
next_count=count+4'd1;
else
next_count=count;
end

[email protected](posedge clock)
begin
if(reset)
count<=4'd0;
else
count<=next_count;
end
endmodule


module test(clock,reset,count);
input clock, reset;
output [3:0] count;
reg [3:0] count;
always @(clock)
counter(clock, reset, count);
endmodule

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  #2 (permalink)  
Old 06-07-2007, 04:18 PM
Jonathan Bromley
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Posts: n/a
Default Re: verilog HDL problem

On Thu, 07 Jun 2007 10:15:56 -0000, babu <[email protected]> wrote:

>what is the error in the following code.


You're thinking of a module as if it were a procedure.
Oh, and a bunch of other stuff that suggests you were
awake during the Counter Design class, but dozing through
the Testbench class :-)

> how can i call another module in always block?


You cannot. You don't "call" a module; you instantiate it.
A module instance just exists, sitting there, doing what it's
supposed to do, for the entire life of the simulation.
You can "call" functions and tasks (Verilog procedures),
but not modules.

>module counter(clock, reset, count);

Looks about right. A counter that counts
each time the clock ticks. See many, many
discussions here and elsewhere for an explanation
of why you're wasting effort and keystrokes by
separating the combinational logic and the
registers into two always blocks.
>endmodule


>module test(clock,reset,count);


Tell me: If you saw a test bench, and the test bench had
a bunch of wires hanging out of it, what would you think?
I *hope* you would think that some idiot forgot to connect
those wires to the appropriate test equipment. That's why
top-level test bench modules have no ports. Such ports
would represent wires that *should* be connected to some
internal part of the test bench.

>input clock, reset;
>output [3:0] count;
>reg [3:0] count;
>always @(clock)
> counter(clock, reset, count);


This is as wrong as it could be.

Who is generating the clock? No-one.
Who is generating the reset? No-one.
Who is examining the "count" output from the counter? No-one.

Let's try again.

// This testbench is COPYRIGHT. Please contact the author
// for licensing information. Typical license fees are
// $0.0001 for a lifetime commercial use license, but for
// academic use please note our special rate of $2500.00
// for each copy that receives a B grade or better.
// Serious legal consequences will follow any use of this
// code that does not incorporate this notice in full.
//
module test; // No ports. The testbench is self-contained.

// We need signals that will connect to the counter under test.
reg test_clock, test_reset; // I will drive these signals.
wire [3:0] test_count; // The counter under test will drive this.

// We need an instance of the device under test.
counter DUT (
.clock(test_clock),
.reset(test_reset),
.count(test_count)
);

// We need a signal generator for the clock.
// Create only 100 clock cycles and then stop.
// This will cause the simulation to stop automatically.
initial begin
test_clock = 0;
repeat (200) test_clock = ~test_clock;
end

// We need a signal generator for the reset.
initial begin
test_reset = 1;
repeat (5) @(negedge test_clock);
test_reset = 0;
end

// We better check what the device is doing.
initial begin : checker
integer clock_count;
clock_count = 0;
forever @(posedge test_clock) begin
clock_count = clock_count + 1;
$display("Cycle %0d: reset = 'b%b, count = 'b%b",
clock_count, test_reset, test_count);
end
end
endmodule

Enjoy.
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services

Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
[email protected]
http://www.MYCOMPANY.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.
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  #3 (permalink)  
Old 06-07-2007, 08:13 PM
babu
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Posts: n/a
Default Re: verilog HDL problem

On Jun 7, 8:18 pm, Jonathan Bromley <[email protected]>
wrote:
> On Thu, 07 Jun 2007 10:15:56 -0000, babu <[email protected]> wrote:
> >what is the error in the following code.

>
> You're thinking of a module as if it were a procedure.
> Oh, and a bunch of other stuff that suggests you were
> awake during the Counter Design class, but dozing through
> the Testbench class :-)
>
> > how can i call another module in always block?

>
> You cannot. You don't "call" a module; you instantiate it.
> A module instance just exists, sitting there, doing what it's
> supposed to do, for the entire life of the simulation.
> You can "call" functions and tasks (Verilog procedures),
> but not modules.
>
> >module counter(clock, reset, count);

>
> Looks about right. A counter that counts
> each time the clock ticks. See many, many
> discussions here and elsewhere for an explanation
> of why you're wasting effort and keystrokes by
> separating the combinational logic and the
> registers into two always blocks.
>
> >endmodule
> >module test(clock,reset,count);

>
> Tell me: If you saw a test bench, and the test bench had
> a bunch of wires hanging out of it, what would you think?
> I *hope* you would think that some idiot forgot to connect
> those wires to the appropriate test equipment. That's why
> top-level test bench modules have no ports. Such ports
> would represent wires that *should* be connected to some
> internal part of the test bench.
>
> >input clock, reset;
> >output [3:0] count;
> >reg [3:0] count;
> >always @(clock)
> > counter(clock, reset, count);

>
> This is as wrong as it could be.
>
> Who is generating the clock? No-one.
> Who is generating the reset? No-one.
> Who is examining the "count" output from the counter? No-one.
>
> Let's try again.
>
> // This testbench is COPYRIGHT. Please contact the author
> // for licensing information. Typical license fees are
> // $0.0001 for a lifetime commercial use license, but for
> // academic use please note our special rate of $2500.00
> // for each copy that receives a B grade or better.
> // Serious legal consequences will follow any use of this
> // code that does not incorporate this notice in full.
> //
> module test; // No ports. The testbench is self-contained.
>
> // We need signals that will connect to the counter under test.
> reg test_clock, test_reset; // I will drive these signals.
> wire [3:0] test_count; // The counter under test will drive this.
>
> // We need an instance of the device under test.
> counter DUT (
> .clock(test_clock),
> .reset(test_reset),
> .count(test_count)
> );
>
> // We need a signal generator for the clock.
> // Create only 100 clock cycles and then stop.
> // This will cause the simulation to stop automatically.
> initial begin
> test_clock = 0;
> repeat (200) test_clock = ~test_clock;
> end
>
> // We need a signal generator for the reset.
> initial begin
> test_reset = 1;
> repeat (5) @(negedge test_clock);
> test_reset = 0;
> end
>
> // We better check what the device is doing.
> initial begin : checker
> integer clock_count;
> clock_count = 0;
> forever @(posedge test_clock) begin
> clock_count = clock_count + 1;
> $display("Cycle %0d: reset = 'b%b, count = 'b%b",
> clock_count, test_reset, test_count);
> end
> end
> endmodule
>
> Enjoy.
> --
> Jonathan Bromley, Consultant
>
> DOULOS - Developing Design Know-how
> VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services
>
> Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
> [email protected]://www.MYCOMPANY.com
>
> The contents of this message may contain personal views which
> are not the views of Doulos Ltd., unless specifically stated.


Many many thanks
May you live long
Bye
Nasif

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  #4 (permalink)  
Old 06-09-2007, 03:37 PM
Jonathan Bromley
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Posts: n/a
Default Re: verilog HDL problem

On Thu, 07 Jun 2007 11:13:21 -0700,
babu <[email protected]> wrote:

> May you live long


I already have ...
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services

Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
[email protected]
http://www.MYCOMPANY.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.
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