FPGA Central

I have an issue with the verilog generate statement. Now my top level
block called top_module is instantiating the low level block module1
as below

module top_level(
.........
.........
parameter DBGATTN = 0;
....
...

block1 #(
.DBGATTN_WIDTH(DBGATTN),
.........
......
endmodule

------------------------------------------------------------------------------------



module block1(
....
.....

parameter DBGATTN_WIDTH = 32;

input [DBGATTN_WIDTH-1:0] dbgattn ; // input signal
input t_clk; // clock
input clr; // Debug
register clear bit
output dbgattn_out; // Debug
register status out

wire [DBGATTN_WIDTH-1:0] dbgattnsync;

genvar i;

generate
if (DBGATTN_WIDTH > 0) // generate the logic below only if
DBGATTN_WIDTH > 0
begin
for (i=0 ; i<DBGATTN_WIDTH; i=i+1)
begin :dbgattn
// 2 reg synchronizer used to synchronize i/p signal in tclk domain
one_synchronizer u_one_synch (
.clr_n (1'b1),
.d (dbgattn[i]),
.clk (t_clk),
.q (dbgattnsync[i])
);

// Output from one_synchronizer is fed to datalatch
datalatch u_datalatch(
.piclr (clr),
.pidatasync (dbgattnsync[i]),
.t_clk (t_clk),
.podata_r (dbgattn_r[i])
);
end
end
endgenerate

endmodule



The issue is, when I instantiate block1 with DBGATTN = 0 though I do
not expect any of the generate logic, but still synthesis tool is
generating 32 instances of the generate logic?? Is it because input
[DBGATTN_WIDTH-1:0] dbgattn, becomes input [-1:0] dbgattn when I
pass in DBGATTN_WIDTH as 0? But if thats the case I should get some
error. But synopsys synthesis tool doesn'y complain.

How to resolve this?


Thanks
Trescot

I would expect the behavior would be to try to implement a block with no
logic (which should give an error because the output needs *something*): a
block with a 2-bit dbgattn input port with indicies -1 and 0.

Could it be that a module without any logic produces the module logic based
on the default parameter?

Note that your default is "parameter DBGATTN_WIDTH = 32;" giving the
possibility that the DBGATTN_WIDTH override didn't take for some reason or
other in your code.

What is your expected behavior for DBGATTN_WIDTH = 0 ? If you specify that
output behavior, you might see a difference in the result. Otherwise,
"don't do that."


<[email protected]> wrote in message
news:[email protected] ups.com...
>I have an issue with the verilog generate statement. Now my top level
> block called top_module is instantiating the low level block module1
> as below
>
> module top_level(
> ........
> ........
> parameter DBGATTN = 0;
> ...
> ..
>
> block1 #(
> .DBGATTN_WIDTH(DBGATTN),
> .........
> ......
> endmodule
>
> ------------------------------------------------------------------------------------
>
>
>
> module block1(
> ...
> ....
>
> parameter DBGATTN_WIDTH = 32;
>
> input [DBGATTN_WIDTH-1:0] dbgattn ; // input signal
> input t_clk; // clock
> input clr; // Debug
> register clear bit
> output dbgattn_out; // Debug
> register status out
>
> wire [DBGATTN_WIDTH-1:0] dbgattnsync;
>
> genvar i;
>
> generate
> if (DBGATTN_WIDTH > 0) // generate the logic below only if
> DBGATTN_WIDTH > 0
> begin
> for (i=0 ; i<DBGATTN_WIDTH; i=i+1)
> begin :dbgattn
> // 2 reg synchronizer used to synchronize i/p signal in tclk domain
> one_synchronizer u_one_synch (
> .clr_n (1'b1),
> .d (dbgattn[i]),
> .clk (t_clk),
> .q (dbgattnsync[i])
> );
>
> // Output from one_synchronizer is fed to datalatch
> datalatch u_datalatch(
> .piclr (clr),
> .pidatasync (dbgattnsync[i]),
> .t_clk (t_clk),
> .podata_r (dbgattn_r[i])
> );
> end
> end
> endgenerate
>
> endmodule
>
>
>
> The issue is, when I instantiate block1 with DBGATTN = 0 though I do
> not expect any of the generate logic, but still synthesis tool is
> generating 32 instances of the generate logic?? Is it because input
> [DBGATTN_WIDTH-1:0] dbgattn, becomes input [-1:0] dbgattn when I
> pass in DBGATTN_WIDTH as 0? But if thats the case I should get some
> error. But synopsys synthesis tool doesn'y complain.
>
> How to resolve this?
>
>
> Thanks
> Trescot
>

On Mar 13, 5:44 pm, "John_H" <[email protected]> wrote:
> I would expect the behavior would be to try to implement a block with no
> logic (which should give an error because the output needs *something*): a
> block with a 2-bit dbgattn input port with indicies -1 and 0.
>
> Could it be that a module without any logic produces the module logic based
> on the default parameter?
>
> Note that your default is "parameter DBGATTN_WIDTH = 32;" giving the
> possibility that the DBGATTN_WIDTH override didn't take for some reason or
> other in your code.
>
> What is your expected behavior for DBGATTN_WIDTH = 0 ? If you specify that
> output behavior, you might see a difference in the result. Otherwise,
> "don't do that."
>
> <[email protected]> wrote in message
>
> news:[email protected] ups.com...
>
>
>
> >I have an issue with the verilog generate statement. Now my top level
> > block called top_module is instantiating the low level block module1
> > as below
>
> > module top_level(
> > ........
> > ........
> > parameter DBGATTN = 0;
> > ...
> > ..
>
> > block1 #(
> > .DBGATTN_WIDTH(DBGATTN),
> > .........
> > ......
> > endmodule
>
> > ---------------------------------------------------------------------------*---------
>
> > module block1(
> > ...
> > ....
>
> > parameter DBGATTN_WIDTH = 32;
>
> > input [DBGATTN_WIDTH-1:0] dbgattn ; // input signal
> > input t_clk; // clock
> > input clr; // Debug
> > register clear bit
> > output dbgattn_out; // Debug
> > register status out
>
> > wire [DBGATTN_WIDTH-1:0] dbgattnsync;
>
> > genvar i;
>
> > generate
> > if (DBGATTN_WIDTH > 0) // generate the logic below only if
> > DBGATTN_WIDTH > 0
> > begin
> > for (i=0 ; i<DBGATTN_WIDTH; i=i+1)
> > begin :dbgattn
> > // 2 reg synchronizer used to synchronize i/p signal in tclk domain
> > one_synchronizer u_one_synch (
> > .clr_n (1'b1),
> > .d (dbgattn[i]),
> > .clk (t_clk),
> > .q (dbgattnsync[i])
> > );
>
> > // Output from one_synchronizer is fed to datalatch
> > datalatch u_datalatch(
> > .piclr (clr),
> > .pidatasync (dbgattnsync[i]),
> > .t_clk (t_clk),
> > .podata_r (dbgattn_r[i])
> > );
> > end
> > end
> > endgenerate
>
> > endmodule
>
> > The issue is, when I instantiate block1 with DBGATTN = 0 though I do
> > not expect any of the generate logic, but still synthesis tool is
> > generating 32 instances of the generate logic?? Is it because input
> > [DBGATTN_WIDTH-1:0] dbgattn, becomes input [-1:0] dbgattn when I
> > pass in DBGATTN_WIDTH as 0? But if thats the case I should get some
> > error. But synopsys synthesis tool doesn'y complain.
>
> > How to resolve this?
>
> > Thanks
> > Trescot- Hide quoted text -
>
> - Show quoted text -


Thanks John for the reply. Actually I missed my output assignment.

assign dbgattn_out = (DBGATTN_WIDTH > 0) ? |podata_r : 1'b0;

Since this is an IP, I should have the provision of not to create any
extra logic when my DBGATTN_WIDTH is 0.

[email protected] wrote:
> I have an issue with the verilog generate statement. Now my top level
> block called top_module is instantiating the low level block module1
> as below

<snip>

> module block1(
> ...
> ....
>
> parameter DBGATTN_WIDTH = 32;
<snip>

> The issue is, when I instantiate block1 with DBGATTN = 0 though I do
> not expect any of the generate logic, but still synthesis tool is
> generating 32 instances of the generate logic?? Is it because input
> [DBGATTN_WIDTH-1:0] dbgattn, becomes input [-1:0] dbgattn when I
> pass in DBGATTN_WIDTH as 0? But if thats the case I should get some
> error. But synopsys synthesis tool doesn'y complain.
>
> How to resolve this?
>
>
> Thanks
> Trescot

You can get rid of the symptome without identifying the true cause:

change your default parameter definition to 0.

Suddenly it works.