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-   -   Verilog based PCB design flow? (http://www.fpgacentral.com/group/showthread.php?t=43518)

Petter Gustad 07-20-2003 11:31 AM

Verilog based PCB design flow?
 

Are there any PCB design packages which let you do your PCB layout
using a Verilog netlist as source?

In most PCB CAD programs you'll have to draw a schematics and draw
symbols for each part. I would like to use a Verilog (or even EDIF)
netlist as a base for the PCB layout work. Of course the physical
parameters for each part has to be specified and mapped to their
respective instances in the verilog netlist.

Petter
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Spam Hater 07-20-2003 10:55 PM

Re: Verilog based PCB design flow?
 

Verilog netlist? Do you mean a netlist created from a Verilog
structural representation? If so, OrCAD can do that.


On 20 Jul 2003 12:31:19 +0200, Petter Gustad
<[email protected]> wrote:

>
>Are there any PCB design packages which let you do your PCB layout
>using a Verilog netlist as source?
>
>In most PCB CAD programs you'll have to draw a schematics and draw
>symbols for each part. I would like to use a Verilog (or even EDIF)
>netlist as a base for the PCB layout work. Of course the physical
>parameters for each part has to be specified and mapped to their
>respective instances in the verilog netlist.
>
>Petter



Petter Gustad 07-21-2003 12:19 AM

Re: Verilog based PCB design flow?
 
Spam Hater <[email protected]> writes:

> Verilog netlist? Do you mean a netlist created from a Verilog
> structural representation? If so, OrCAD can do that.


I mean a Verilog netlist I write in a text editor which instantiate
components used on the PCB. I would be happy if somebody could point
me to some documentation (URL's) on how to do this in OrCAD.


Petter

--
A: Because it messes up the order in which people normally read text.
Q: Why is top-posting such a bad thing?
A: Top-posting.
Q: What is the most annoying thing on usenet and in e-mail?

Spam Hater 07-22-2003 05:30 PM

Re: Verilog based PCB design flow?
 

Step 1) Create netlist from Verilog source.
Step 2) Read netlist into PCB editor.

I think you're missing step 1. Verilog is not a netlist; netlists are
created from Verilog.


On 21 Jul 2003 01:19:54 +0200, Petter Gustad
<[email protected]> wrote:

>Spam Hater <[email protected]> writes:
>
>> Verilog netlist? Do you mean a netlist created from a Verilog
>> structural representation? If so, OrCAD can do that.

>
>I mean a Verilog netlist I write in a text editor which instantiate
>components used on the PCB. I would be happy if somebody could point
>me to some documentation (URL's) on how to do this in OrCAD.
>
>
>Petter



Andy Peters 07-24-2003 08:57 PM

Re: Verilog based PCB design flow?
 
Petter Gustad <[email protected]> wrote in message news:<[email protected]>...
> Spam Hater <[email protected]> writes:
>
> > Verilog netlist? Do you mean a netlist created from a Verilog
> > structural representation? If so, OrCAD can do that.

>
> I mean a Verilog netlist I write in a text editor which instantiate
> components used on the PCB. I would be happy if somebody could point
> me to some documentation (URL's) on how to do this in OrCAD.


What you need is a tool that "synthesizes" the Verilog and outputs a
netlist in perhaps Tango (or whatever) format that the PCB layout tool
can import. The tool would have to understand your PCB layout
software's library structure.

I know of a text-based design-entry tool flow but it's based on a
proprietary language. I haven't seen one that uses Verilog or VHDL.

If you were to use Verilog or VHDL for this sort of thing, I think
you'd have to use a subset of the language. For instance, a schematic
doesn't understand anything about timing. Basically, you'd use the
HDL to instantiate blocks and wire them together.

But that's actually OK. Consider that the HDL simulator could pull
real models from a library so you could simulate your whole board.
The PCB netlister tool would simply pull a footprint from the library.
And imagine using generates to instantiate a whole bunch of memory
chips, rather than having to place each one on the schematic and wire
them up.

Also, using an HDL would let you do some very useful things that are
difficult and cumbersome to do from a schematic. For example, say you
have a design that can accept different sized (as in capacity, not
footprint!) memory devices. You can use generates and parameters to
create stuffing guides with the different parts as needed.

I guess the final advantage is that the design entry is text based.
Source-control programs work without problems. Searching files for
instances of whatever is a piece of cake. And there's no worries
about your schematic tools vendor changing the format, or going out of
business!

---a


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