FPGA Central - World's 1st FPGA / CPLD Portal

FPGA Central

World's 1st FPGA Portal

 

Go Back   FPGA Groups > NewsGroup > Verilog

Verilog comp.lang.verilog newsgroup / usenet

Reply
 
LinkBack Thread Tools Display Modes
  #1 (permalink)  
Old 06-27-2003, 04:38 AM
New to Verilog
Guest
 
Posts: n/a
Default Verilog Assertion Problem

Hi,

I have to write a module which has tons of parameters. So for
simplicity lets just focus on one paramter. Lets say the parameter
is called: NRCB_G. This parameter is a integer and it's valid values
are only 2, 4 or 8. In order to guarantee correct hook-up of the
module at the higher level (selection of the parameter) I would like
to embedd an assertion inside the module which checks the value given
to the parameter. This assertion should fire if the parameter is not
set to 2, 4 or 8.

I chose to use the assert_proposition assertion and this is how I use
it:

assert_proposition #(0, 0, "CONFIG_ERROR : Valid Values for NRCB_G parameter are : 2, 4 or 8")
NRCB_G_RANGE_CHECK (1'b1, NRCB_G == 2 || NRCB_G == 4 || NRCB_G == 8);

So in case i set the parameter to 2, 4 or 8 everything is fine, the
assertion keeps quite. Now when I chose a value outside the valid range,
the assertion still doesn't fire. So my question is, do i pick
the wrong assertion for these kind of checks, or in case this is the
appropriate assertion, am I using it the wrong way or is there another
switch/parameter I need to set inorder to enable the assertion ?

Thanks in advance for your response !!

Reply With Quote
  #2 (permalink)  
Old 06-27-2003, 10:42 AM
Srinivasan Venkataramanan
Guest
 
Posts: n/a
Default Re: Verilog Assertion Problem

Hi,
I suspect 2 things

1. You didn't define ASSERT_ON (required by the OVL modules, else the
assertion is typically masked form the compiler).
2. Since your inputs to the assert_proposition instances are constants, you
have a race condition by which the always block within the OVL doesn't get
triggered, NC seems to work fine in your example, which simulator do you
use?

HTH,
Srinivasan

--
Srinivasan Venkataramanan
Senior Verification Engineer
Software & Silicon Systems India Pvt Ltd. - an Intel company
Bangalore, India

http://www.noveldv.com http://www.deeps.org

I don't speak for Intel
"New to Verilog" <[email protected]> wrote in message
news:[email protected]
> Hi,
>
> I have to write a module which has tons of parameters. So for
> simplicity lets just focus on one paramter. Lets say the parameter
> is called: NRCB_G. This parameter is a integer and it's valid values
> are only 2, 4 or 8. In order to guarantee correct hook-up of the
> module at the higher level (selection of the parameter) I would like
> to embedd an assertion inside the module which checks the value given
> to the parameter. This assertion should fire if the parameter is not
> set to 2, 4 or 8.
>
> I chose to use the assert_proposition assertion and this is how I use
> it:
>
> assert_proposition #(0, 0, "CONFIG_ERROR : Valid Values for NRCB_G

parameter are : 2, 4 or 8")
> NRCB_G_RANGE_CHECK (1'b1, NRCB_G == 2 || NRCB_G == 4 || NRCB_G ==

8);
>
> So in case i set the parameter to 2, 4 or 8 everything is fine, the
> assertion keeps quite. Now when I chose a value outside the valid range,
> the assertion still doesn't fire. So my question is, do i pick
> the wrong assertion for these kind of checks, or in case this is the
> appropriate assertion, am I using it the wrong way or is there another
> switch/parameter I need to set inorder to enable the assertion ?
>
> Thanks in advance for your response !!
>



Reply With Quote
Reply

Bookmarks

Thread Tools
Display Modes

Posting Rules
You may not post new threads
You may not post replies
You may not post attachments
You may not edit your posts

BB code is On
Smilies are On
[IMG] code is On
HTML code is Off
Trackbacks are On
Pingbacks are On
Refbacks are On



All times are GMT +1. The time now is 08:50 AM.


Powered by vBulletin® Version 3.8.0
Copyright ©2000 - 2019, Jelsoft Enterprises Ltd.
Search Engine Friendly URLs by vBSEO 3.2.0
Copyright 2008 @ FPGA Central. All rights reserved