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Old 11-10-2005, 09:46 PM
Chris Briggs
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Default using array ports in SV

I have a SystemVerilog question. The LRM says a module port can be an
array, but I can't figure out the syntax to connect to it in the
instantation.

Example:

module foo;
wire [7:0] dat0;
wire [7:0] dat1;

bar bar0(.baz ({dat1, dat0}));
endmodule // foo

module bar(input wire [7:0] baz [2]);

endmodule // bar

When I run that through Questa, I get an error:
# ** Error: (vsim-3843) array_in.sv(5): Illegal packed type to unpacked
type connection for port 'baz'.

I've tried several variations on that but haven't gotten it right. How
are you supposed to connect different signals to elements of an input
array? Do I have to put them in an array first?

TIA.

-cb

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Old 11-11-2005, 01:35 AM
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Default Re: using array ports in SV

The problem is that your {dat1, dat0} is being treated as a
concatenation. The Accellera standard had a problem that the syntax
for constructing an array was ambiguous with the existing Verilog
syntax for concatenation. The (just approved) IEEE standard fixed this
by changing the syntax for constructing an array or structure value.
Your tool might accept that new syntax.

The fully qualified syntax preceeds the curly braces with a type
qualifier, datatype', where datatype is the name of the array or
structure type. For cases like this one, where the type can be
determined from the type on the other side of the port, you can leave
the datatype off. So the short-hand syntax is '{dat1, dat0}. The '
character still indicates that this is not an ordinary concatenation.

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