FPGA Central - World's 1st FPGA / CPLD Portal

FPGA Central

World's 1st FPGA Portal

 

Go Back   FPGA Groups > NewsGroup > Verilog

Verilog comp.lang.verilog newsgroup / usenet

Reply
 
LinkBack Thread Tools Display Modes
  #1 (permalink)  
Old 08-03-2005, 11:04 PM
Fei
Guest
 
Posts: n/a
Default Urgent question: how to find I/O port dependency in a Verilog code?

Here is a question:
"Given a combinational circuit, for each primary output, find the
number of primary inputs that this output depends on."

It is easy to do structual analysis for a small-size circuit. But for a
circuit with million gates, we need to find a effecient way.

Now assume a gate-level Verilog code for this circuit is given, I plan
to write a script (e.g., Perl) to scan this Verilog code, then for each
output, trace back to find the primary input on which it depends. But I
am new to both Perl and Verilog.
So could you please give me any suggestion or any script example for
references? or is there other way to address this problem effeceintly?

Thanks very much!
Fei

Reply With Quote
  #2 (permalink)  
Old 08-04-2005, 12:10 AM
Fei
Guest
 
Posts: n/a
Default Re: Urgent question: how to find I/O port dependency in a Verilog code?

And also, can Verilog PLI deal with this problem?


Please give me a hint... Thanks!
Fei

Reply With Quote
  #3 (permalink)  
Old 08-04-2005, 01:01 AM
Carl W.
Guest
 
Posts: n/a
Default Re: Urgent question: how to find I/O port dependency in a Verilogcode?

Fei wrote:
> Here is a question:
> "Given a combinational circuit, for each primary output, find the
> number of primary inputs that this output depends on."
>
> It is easy to do structual analysis for a small-size circuit. But for a
> circuit with million gates, we need to find a effecient way.
>
> Now assume a gate-level Verilog code for this circuit is given, I plan
> to write a script (e.g., Perl) to scan this Verilog code, then for each
> output, trace back to find the primary input on which it depends. But I
> am new to both Perl and Verilog.
> So could you please give me any suggestion or any script example for
> references? or is there other way to address this problem effeceintly?


Look up "Boolean Decision Diagrams" (aka BDDs) on your
favorite search engine; I even saw a web page once which compared
several BDD packages (I don't have the URL handy).

If I were trying to solve this problem, I would use Perl (or
a C lexer/parser package) to scan the Verilog and pipe the output
to a BDD package, asking it to build BDDs for each of the module
output ports. From there, it shouldn't be too hard to write code
to "walk the BDD" for each output to see if an input is ignored
or if it "matters" to the output. The BDD package does most of
the hard work of reducing the Boolean logic so -- if an input
doesn't affect the output -- the BDD package should either
eliminate it from the BDD or figure out that the '0' & '1'
pointers of that input's node in the BDD tree point to the same
place.

I haven't worked with BDDs for several years; early BDD
packages created very large BDDs (running out of memory) for
parity trees & other circuits which generated a lot of XOR
gates/functions. If your Verilog has large parity trees, adders,
etc. -- anything which generates a lot of XOR functions, you may
wish to benchmark different BDD packages with large XOR circuits
to see which ones make the most sense for your application.
Reply With Quote
  #4 (permalink)  
Old 08-06-2005, 08:26 PM
Ira Baxter
Guest
 
Posts: n/a
Default Re: Urgent question: how to find I/O port dependency in a Verilog code?


"Fei" <[email protected]> wrote in message
news:[email protected] oups.com...
> "Given a combinational circuit, for each primary output, find the
> number of primary inputs that this output depends on."
>
> It is easy to do structual analysis for a small-size circuit.


You mean by visual inspection.

>But for a circuit with million gates, we need to find a effecient way.
>
> Now assume a gate-level Verilog code for this circuit is given, I plan
> to write a script (e.g., Perl) to scan this Verilog code, then for each
> output, trace back to find the primary input on which it depends. But I
> am new to both Perl and Verilog.
> So could you please give me any suggestion or any script example for
> references? or is there other way to address this problem effeceintly?


A PERL script "parse" Verilog will likely be unreliable. In a million
lines of code, "everything happens", which means you will
very likely will need a full Verilog parser just to make sure
that you don't misinterpret the source text.

Ideally, you'd have a Verilog parser, and could walk over the syntax
tree representing the expression for each output to enumerate the inputs.
Of course, symbols in that expression may represent other combinational
outputs,
thus you'll have to through a fixpoint procedure to arrive at just
the inputs values.

A full Verilog parser (including SystemVerilog ) that will build
you the trees is commercially available from:
http://www.semdesigns.com/Products/F...gFrontEnd.html.

--
Ira D. Baxter, Ph.D., CTO 512-250-1018
Semantic Designs, Inc. www.semdesigns.com


Reply With Quote
  #5 (permalink)  
Old 08-07-2005, 06:57 PM
Guest
 
Posts: n/a
Default Re: Urgent question: how to find I/O port dependency in a Verilog code?

A million gates of gate-level Verilog is likely to be the output of
some synthesis tool, and probably only uses a very small subset of the
language, e.g. instantiations of library components and nothing else.
The OP only needs to identify combinatorial logic, and storage elements
(ffs, latches and rams).

Someone experienced in both Perl and Verilog (and the library used)
could probably implement the parser for the required subset of the
language from scratch in about a day. (Well, that's how long it took
the last time I wrote one.)

Regards,
Allan

Reply With Quote
Reply

Bookmarks

Thread Tools
Display Modes

Posting Rules
You may not post new threads
You may not post replies
You may not post attachments
You may not edit your posts

BB code is On
Smilies are On
[IMG] code is On
HTML code is Off
Trackbacks are On
Pingbacks are On
Refbacks are On


Similar Threads
Thread Thread Starter Forum Replies Last Post
Overheads of 4-port over 2-port SRAM John T. Goodman Verilog 0 01-25-2005 05:26 PM
making output port to bi-directional port! Vick Verilog 0 12-16-2004 07:14 AM
Making output-port to bi-directional-port! Vick Verilog 5 12-15-2004 07:03 AM
4-stage fixed-point binomial pipeline >>>>> urgent help dolly Verilog 5 11-09-2004 05:29 AM
Where can I find a free Verilog PLI 2.0 reference?Thanks Lee Verilog 0 05-14-2004 09:10 PM


All times are GMT +1. The time now is 06:15 PM.


Powered by vBulletin® Version 3.8.0
Copyright ©2000 - 2021, Jelsoft Enterprises Ltd.
Search Engine Friendly URLs by vBSEO 3.2.0
Copyright 2008 @ FPGA Central. All rights reserved