FPGA Central

does anybody know how to design "bundled data interface" using verilog
HDL?

here two combinational blocks talk to each other using "request" and
"acknowledge" signals.

thank you

Looks like you trying to simulate asynchronous state machine, then I
feel you have to use delays to make it work in a particular sequence.

you are right. but what i am trying to here is implement asynchronous
micropipeline explained in follwing paper.
http://f-cpu.seul.org/new/micropipelines.pdf. this paper is from Ivan
Sutherland of Sun Microsystems.

here he has explained the bundled data convention and then he has given
control circuit to make it work. now i have tried to implement it with
verilog but i am not sure if my code is working fine.

if you could please tell me how to control those signals in verilog, it
would be really helpful.

if you could please help me in implementing circuits which are on page
number 726 and 729

i have written verilog code for following logic. if someone can tell if
is it right?? i am not allowed to use clock here. it has to be latch
based design.

"IF predecessor and successor differ in state
THEN copy predecessor's state
ELSE hold present state."

`timescale 1 ns / 100 ps
module c0(R_in,A_1,A_in,Reset);
input R_in;
input A_1;
output A_in;
input Reset;
reg A_in;
reg A1;

always @ (Reset or R_in or A_1)
begin
A1 = ~A_1;
if (Reset == 0)
begin
A_in = 0;
end
else if (R_in != A1)
begin
A_in = R_in;
end
end

endmodule

the above is fine if A1 represents the previous state of A_in.

i got it. its working fine. thank you.