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Old 12-01-2005, 11:20 PM
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Default Timing analysis for latch-based design in Design Compiler.

In Design Compiler, a balanced relative slack is prefered for
latch-based design. Can anybody tell me why?I don't quite understand
why it can reduce delay costs and optimize near-critical path.

Usually we just need to reduce the critical path, why near-critical
path is needed here?


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Old 12-02-2005, 04:06 AM
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Default Re: Timing analysis for latch-based design in Design Compiler.

Latch-based design is not timing friendly. In some cases it can solve
critical path. For example, some posedge FlipFlops' outputs go through
combinational logic and the destination side is a negedge FF. The path
is half clock cycle, if you replace the negedge FF by a low enable
latch, you can borrow time from the next stage of the pipeline. But you
have to make sure next stage is not time critical.

Netlist debug/ECO in GUI mode.

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