"CupOfWater" <
[email protected]> wrote in message
news:
[email protected] om...
> Hi,
>
> I'm wondering if I may be not using tasks correctly? I have some code
> that is suppose to toggle certain signals at certain times to meet
> timing specs for my device that I'm testing. I'm using modelsim 6.2
> as the simulator.
>
> task cmdlatch;
> inout cle, cebar, webar, ale;
> inout [7:0] io;
> input [7:0] cmd;
> begin
> cle = 1; cebar = 0; webar = 1; ale = 0;
> #10 begin
> cle = 1; cebar = 0; webar = 0; ale = 0;
> end
[... more stuff ...]
> so in modelsim I'm expecting the waveforms to toggle, but instead the
> signals are stuck on low. I also tried using "<=" inside the task,
> but the situation does not change. Any help would be appreciated.
This is a standard Verilog "gotcha", and it's particularly painful
for people migrating from VHDL where procedures can have signal-class
parameters.
In Verilog, task arguments are copied IN to the task at the moment
of task call ("enabling", in the bizarre Verilog jargon) and copied
OUT to the actual arguments at the moment when the task exits.
Any assignments to the formal arguments during the life of the
task will have NO effect on the registers that you passed as
actual arguments in the task call.
The correct approach is to pass in to the task only those
arguments that will affect the way it works, and have it
work directly on registers declared within the enclosing
module...
module GoodTask;
reg [7:0] Data;
task driveData;
input [7:0] value;
begin
Data = 8'bz;
#10 Data = value; // Manipulates the module-level Data reg
#10 Data = 8'bz;
#10;
end
endtask
initial begin
driveData(8'd5); // Wiggles Data successfully
driveData(8'd200);
end
endtask
module BadTask;
reg [7:0] Data;
task driveData;
input [7:0] value;
inout [7:0] Signal;
begin // Inout argument is copied in to Signal here
Signal = 8'bz; //
#10 signal = value; // Manipulates only the local reg Signal
#10 Signal = 8'bz; //
#10;
end // Copies 8'bz back to the argument
endtask
initial begin
driveData(8'd5, Data); // Doesn't wiggle Data
end
endtask
If you want a task like this to be able to work on many different
signals, the correct approach is:
package it in a module;
give the module a port for the signals your task will manipulate;
make the task operate on the module's ports;
wire up an instance of the module to each signal;
use hierarchical names to call in to the task
from the module that instantiated the task's wrapper module.
Hierarchical names are generally
not synthesisable but are very useful for test benches.
--
Jonathan Bromley, Consultant
DOULOS - Developing Design Know-how
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