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Old 12-07-2008, 07:50 PM
tolaj
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Default Systemverilog SVA $stable question

I'm learning SVA on my own, and I had a question about $stable.

$stable: if used in a concurrent-assertion, is the stability check performed
continuously (at all times), or only on the triggering clock-edge?

1) data_valid => high_signal [*5] => !data_valid;

2) data_valid => $stable(high_signal) [*5] => !data_valid;

I know that (1) is insufficient. high_signal could glitch between
clock-transitions, and
this assertion can't detect glitches.

So is (2) a solution?


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