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Old 05-30-2006, 08:56 AM
Davy
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Default SystemVerilog Coverage iff

Hi all,

I am new to SystemVerilog.
My friend told me TYPE1 can be compiled and TYPE2 cannot be compiled,
is it right?
BTW, I use cadence tools.

covergroup [email protected](negedge CLK);
one_sig: coverpoint one_sig
{
//TYPE1
bins a = {1} iff(vaild )
//TYPE2
bins a = {1} iff(vaild ==2);
... ...
}

Best regards,
Davy

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  #2 (permalink)  
Old 05-30-2006, 01:56 PM
Ajeetha
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Default Re: SystemVerilog Coverage iff

Hi Davy,
LRM allows the Type 2 also. The following code works with VCS.

module cov_test ;
logic CLK;
logic a;
integer valid;
logic one_sig;
covergroup [email protected](negedge CLK);
coverpoint one_sig
{
//TYPE1
bins a = {1} iff(valid );
//TYPE2
bins a1 = {1} iff(valid ==2);
}
endgroup : cg0
endmodule : cov_test

Which version of NC did you use ?

HTH,
Ajeetha, CVC
www.noveldv.com

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