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Old 11-08-2005, 07:56 AM
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Default system verilog

System verilog virtual interface problem:

A question related virtual interfaces for system verilog:

Can a module have virtual interfaces? It does not make sense for a
module to have virtual interface, as module represents a real
synthesizable, meanwhile virtual interface does not. Can someone shed
light on it?

Since, a virtual interface can be used in the program, can we have ref
obj's for virtual interfaces? Beacuse, programs cannot have instance
(they are leaf level), is my statment valid?

Ankur K

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