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  #1 (permalink)  
Old 03-09-2005, 09:35 AM
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Default Synthesis Quesiton (single module vs. multiple modules)


I have a question regarding synthesizing a verilog project.
Let's say we have 5 modules in a project and want to synthesize them. My
question is that if there's any difference between "placing all 5 modules
in a single .v file" and "having five .v files so each file consists of
one module".

Is there any difference between the two methods? (such as number of
modules created, P & R or timing)

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  #2 (permalink)  
Old 03-09-2005, 04:18 PM
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Default Re: Synthesis Quesiton (single module vs. multiple modules)

If you are using ungroup -all in ur script. then it doesnt make a

logic optmisations will not cross module boundary unless ungroup
command is used. also pin(hierachical) names will be preserved in

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  #3 (permalink)  
Old 03-10-2005, 08:51 AM
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Default Re: Synthesis Quesiton (single module vs. multiple modules)

You saving in terms of resources will be meagre but then you will be
sacrificing the modularity of the design.

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