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Old 03-23-2006, 09:25 PM
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Default Synthesis of delay

Is it possible to infer or synthesise delay in verilog, my AMS 0.35um
standard cell library has delay elements of around 1ns 2ns 3ns, but no way
to map to them. Any ideas?

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  #2 (permalink)  
Old 03-23-2006, 10:13 PM
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Default Re: Synthesis of delay

Ca't you simply instantiate the cells? If it the cell
was named ams35_delay1ns in your library, simply

ams35_delay1ns u0_ams35_delay1ns (.o (delayed_signal), .i
(input_signal) );

John Providenza

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