software suggestion needed
 

Hi everyone,
I am looking for a piece of software which would allow me verify my
pipelined implementation of an existing algorithm implemented in an
HDL. My original algorithm (& naive implementation in Verilog) uses
tens of multipliers. What I am doing is to use limited number of
multipliers, extra storage for intermediate variables and a sequential
state-machine which calculates one output every N cycles. The issue is
that implementation of this new implementation is quite tedious and
verification is also time-consuming. I am looking for a program which
can verify that the sequential implementation is correct in terms of
scheduled operations. I am even willing to implement it in a language
other than verilog and re-implement it in verilog when I get the
shceduling right (of course a translator from the language of the tool
to verilog would be very helpful here :-). Any suggestions ?

Thanks ahead.

Re: software suggestion needed
 

mk wrote:
> Hi everyone,
> I am looking for a piece of software which would allow me verify my
> pipelined implementation of an existing algorithm implemented in an
> HDL. My original algorithm (& naive implementation in Verilog) uses
> tens of multipliers. What I am doing is to use limited number of
> multipliers, extra storage for intermediate variables and a sequential
> state-machine which calculates one output every N cycles. The issue is
> that implementation of this new implementation is quite tedious and
> verification is also time-consuming. I am looking for a program which
> can verify that the sequential implementation is correct in terms of
> scheduled operations. I am even willing to implement it in a language
> other than verilog and re-implement it in verilog when I get the
> shceduling right (of course a translator from the language of the tool
> to verilog would be very helpful here :-). Any suggestions ?
>
> Thanks ahead.

You may want to consider using Python. It's often used to develop
algorithms.

You could use unit testing (with the unittest module) to verify all
aspects of the algorithm.

With MyHDL (a package to use Python as a HDL) you could refine it
into a hardware design, and verify using the same unit tests.
See the link below.

A MyHDL model can be converted automatically to Verilog. (This
works only if certain coding constraints are met.)

Regards, Jan

--
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
Losbergenlaan 16, B-3010 Leuven, Belgium
From Python to silicon:
http://myhdl.jandecaluwe.com