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Old 05-16-2007, 07:34 AM
himassk
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Default Single clock pulse transfer b/w clock domain

Hi,

Please suggest me how to transfer a single clockwide pulse from high
frequency clock domain and create a single clockwide pulse in a slow
clock domain?
What are different methods available?

Thanks in advance.

Regards,
Himassk.

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  #2 (permalink)  
Old 05-16-2007, 07:47 AM
Mark McDougall
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Default Re: Single clock pulse transfer b/w clock domain

himassk wrote:

> Please suggest me how to transfer a single clockwide pulse from high
> frequency clock domain and create a single clockwide pulse in a slow
> clock domain?
> What are different methods available?


One method I've used is to stretch the pulse in the HF domain enough for
the LF domain to see it, then implement a rising-edge-detect in the LF domain.

Regards,

--
Mark McDougall, Engineer
Virtual Logic Pty Ltd, <http://www.vl.com.au>
21-25 King St, Rockdale, 2216
Ph: +612-9599-3255 Fax: +612-9599-3266
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Old 05-17-2007, 12:18 AM
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Default Re: Single clock pulse transfer b/w clock domain

On May 15, 10:34 pm, himassk <[email protected]> wrote:
> Hi,
>
> Please suggest me how to transfer a single clockwide pulse from high
> frequency clock domain and create a single clockwide pulse in a slow
> clock domain?
> What are different methods available?
>
> Thanks in advance.
>
> Regards,
> Himassk.


If you KNOW that the positive edge of the low frequency clock will not
occur at the same time as the high-frequency pulse, then you can use
the HF pulse to asynchronously set a flip flop...
------------------------
[email protected](posedge clk_lf or posedge pulse_hf)
if (pulse_hf)
pulse_lf <= 1;
else
pulse_lf <= 0;
------------------------
This creates a pulse less than one cycle of the low frequency clock.
If it had to be exactly 1 clock cycle wide you could clean it up using
another flip flop.

In most cases though it can't be guaranteed that the low frequency
clock won't occur at the same time as the high frequency pulse. In
this case, you could delay the HF pulse and detect the pulse as
before...
------------------------
// detect early pulse
[email protected](posedge clk_lf or posedge pulse_hf_early)
if (pulse_hf_early)
pulse_lf_early <= 1;
else
pulse_lf_early <= 0;

// detect late pulse
[email protected](posedge clk_lf or posedge pulse_hf_late)
if (pulse_hf_late)
pulse_lf_late <= 1;
else
pulse_lf_late <= 0;

assign pulse_lf = pulse_lf_late || pulse_lf_early;
------------------------
This produces a pulse with a width between a fraction of the low
frequency clock and two times the low frequency clock. This signal
could be passed through a rising edge detector to produce a pulse
exactly one cycle long.

The final case would be if the low frequency clock is derived from the
high frequency clock. In this case...
------------------------
[email protected](posedge clk_lf or posedge pulse_hf)
if (pulse_hf)
pulse_lf <= 1;
else
pulse_lf = !pulse_hf;
------------------------

David Walker

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Old 05-18-2007, 08:10 AM
Ralf Hildebrandt
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Default Re: Single clock pulse transfer b/w clock domain

himassk schrieb:

> Please suggest me how to transfer a single clockwide pulse from high
> frequency clock domain and create a single clockwide pulse in a slow
> clock domain?
> What are different methods available?


What about a handshake flipflop running with hf_clock? Set the
handshake-FF if there is a hf-clock pulse. If the handshake-FF is set,
then the lf-clock pulse can be generated. If the lf-clock pulse is
active, then reset the handshake-FF (synchronously).
For unknown clock frequencies of if hf_cloock is not much faster than
lf_clock you need two handshake-FFs for one direction: one FF for set
and one for reset.
Transferring the pulse in both directions you need 4 handshake-FFs.

Ralf
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